Inventor
BOMBERGER CORY
US32 patents
Patents
32 patentsUS11522048B2Dec 6, 2022
Gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs
INTEL CORP6 citations86
US12272727B2Apr 8, 2025
Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures
INTEL CORP2 citations74
US12021149B2Jun 25, 2024
Fin smoothing and integrated circuit structures resulting therefrom
INTEL CORP2 citations73
US11682731B2Jun 20, 2023
Fin smoothing and integrated circuit structures resulting therefrom
INTEL CORP2 citations73
US11328988B2May 10, 2022
Top gate recessed channel CMOS thin film transistor in the back end of line and methods of fabrication
INTEL CORP2 citations73
US11164785B2Nov 2, 2021
Three-dimensional integrated circuits (3DICs) including upper-level transistors with epitaxial source and drain material
INTEL CORP2 citations73
US12027585B2Jul 2, 2024
Source or drain structures with low resistivity
INTEL CORP2 citations72
US11990513B2May 21, 2024
Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures
INTEL CORP2 citations72
US11532706B2Dec 20, 2022
Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures
INTEL CORP3 citations72
US11244943B2Feb 8, 2022
Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material
INTEL CORP2 citations72
US11735630B2Aug 22, 2023
Integrated circuit structures with source or drain dopant diffusion blocking layers
INTEL CORP2 citations71
US11532734B2Dec 20, 2022
Gate-all-around integrated circuit structures having germanium nanowire channel structures
INTEL CORP3 citations71
US12027417B2Jul 2, 2024
Source or drain structures with high germanium concentration capping layer
INTEL CORP2 citations69
US11887988B2Jan 30, 2024
Thin film transistor structures with regrown source and drain
INTEL CORP1 citations63
US12388011B2Aug 12, 2025
Top gate recessed channel CMOS thin film transistor and methods of fabrication
INTEL CORP0 citations62
US12237420B2Feb 25, 2025
Fin smoothing and integrated circuit structures resulting therefrom
INTEL CORP0 citations62
US12159901B2Dec 3, 2024
Gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs
INTEL CORP0 citations62
US11996404B2May 28, 2024
Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material
INTEL CORP0 citations62
US11984449B2May 14, 2024
Channel structures with sub-fin dopant diffusion blocking layers
INTEL CORP0 citations62
US11929320B2Mar 12, 2024
Top gate recessed channel CMOS thin film transistor in the back end of line and methods of fabrication
INTEL CORP0 citations62
US11521968B2Dec 6, 2022
Channel structures with sub-fin dopant diffusion blocking layers
INTEL CORP0 citations62
US11450739B2Sep 20, 2022
Germanium-rich nanowire transistor with relaxed buffer layer
INTEL CORP0 citations62
US12575170B2Mar 10, 2026
Low temperature, high germanium, high boron SiGe:B pEPI with a silicon rich capping layer for ultra-low PMOS contact resistivity and thermal stability
INTEL CORP0 citations61
US12439640B2Oct 7, 2025
Reduced contact resistivity with PMOS germanium and silicon doped with boron gate all around transistors
INTEL CORP0 citations61
US11978784B2May 7, 2024
Gate-all-around integrated circuit structures having germanium nanowire channel structures
INTEL CORP0 citations61
US11621325B2Apr 4, 2023
Source or drain structures with low resistivity
INTEL CORP0 citations61
US12426342B2Sep 23, 2025
Low germanium, high boron silicon rich capping layer for PMOS contact resistance thermal stability
INTEL CORP0 citations59
US12598777B2Apr 7, 2026
Low temperature, high germanium, high boron SiGe:B pEPI with titanium silicide contacts for ultra-low PMOS contact resistivity and thermal stability
INTEL CORP0 citations57
US12484272B2Nov 25, 2025
Source or drain structures with relatively high germanium content
INTEL CORP0 citations52
US11374100B2Jun 28, 2022
Source or drain structures with contact etch stop layer
INTEL CORP0 citations52
US11264501B2Mar 1, 2022
Device, method and system for promoting channel stress in a NMOS transistor
INTEL CORP0 citations52
US12520509B2Jan 6, 2026
Diode structure with backside epitaxial growth
INTEL CORP0 citations50