Inventor

CHAO ROBIN HSIN KUO

US29 patents

⚠️ This page may combine multiple inventors who share the name “CHAO ROBIN HSIN KUO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHAO ROBIN HSIN KUO

IBM

Self-aligned inner-spacer replacement process using implantation

Formation of dielectric layer as etch-stop for source and drain epitaxy disconnection

Nanosheet transistor with robust source/drain isolation from substrate

Secure wafer inspection and identification

Self-limiting and confining epitaxial nucleation

Formation of dielectric layer as etch-stop for source and drain epitaxy disconnection

Measuring defectivity by equipping model-less scatterometry with cognitive machine learning

Nanosheet transistor with robust source/drain isolation from substrate

Dielectric isolation in gate-all-around devices

Techniques for vertical FET gate length control

Dielectric isolation in gate-all-around devices

Self-limiting and confining epitaxial nucleation

Undercut control in isotropic wet etch processes

Machine learning enhanced optical-based screening for in-line wafer testing

Predictive multi-stage modelling for complex process control

Inner spacer formation for nanosheet transistors

Replacement-channel fabrication of III-V nanosheet devices

Semiconductor device and method of forming the semiconductor device

Replacement-channel fabrication of III-V nanosheet devices

Replacement-channel fabrication of III-V nanosheet devices

Vertical field-effect transistor including a fin having sidewalls with a tapered bottom profile

Vertical field-effect transistor including a fin having sidewalls with a tapered bottom profile

Long channels for transistors

Self-limiting and confining epitaxial nucleation

Self-aligned inner-spacer replacement process using implantation

Long channels for transistors

Self-aligned inner-spacer replacement process using implantation

Method for quantification of process non uniformity using model-based metrology

ELPIS TECH INC

Techniques for vertical FET gate length control