Inventor
OBRADOVIC BORNA
US24 patents
⚠️ This page may combine multiple inventors who share the name “OBRADOVIC BORNA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SAMSUNG ELECTRONICS CO LTD
11 patentsUS9287357B2Mar 15, 2016
Integrated circuits with Si and non-Si nanosheet FET co-integration with low band-to-band tunneling and methods of fabricating the same
SAMSUNG ELECTRONICS CO LTD66 citations97
US9853114B1Dec 26, 2017
Field effect transistor with stacked nanowire-like channels and methods of manufacturing the same
SAMSUNG ELECTRONICS CO LTD24 citations94
US9647098B2May 9, 2017
Thermionically-overdriven tunnel FETs and methods of fabricating the same
SAMSUNG ELECTRONICS CO LTD42 citations93
US9466669B2Oct 11, 2016
Multiple channel length finFETs with same physical gate length
SAMSUNG ELECTRONICS CO LTD16 citations84
US9960232B2May 1, 2018
Horizontal nanosheet FETs and methods of manufacturing the same
SAMSUNG ELECTRONICS CO LTD7 citations83
US9653287B2May 16, 2017
S/D connection to individual channel layers in a nanosheet FET
SAMSUNG ELECTRONICS CO LTD11 citations81
US9805795B2Oct 31, 2017
Zero leakage, high noise margin coupled giant spin hall based retention latch
SAMSUNG ELECTRONICS CO LTD2 citations73
US9899529B2Feb 20, 2018
Method to make self-aligned vertical field effect transistor
SAMSUNG ELECTRONICS CO LTD5 citations72
US9870940B2Jan 16, 2018
Methods of forming nanosheets on lattice mismatched substrates
SAMSUNG ELECTRONICS CO LTD5 citations72
US10181527B2Jan 15, 2019
FinFet having dual vertical spacer and method of manufacturing the same
SAMSUNG ELECTRONICS CO LTD1 citations62
US9773904B2Sep 26, 2017
Vertical field effect transistor with biaxial stressor layer
SAMSUNG ELECTRONICS CO LTD0 citations47
TEXAS INSTRUMENTS INC
8 patentsUS7718482B2May 18, 2010
CD gate bias reduction and differential N+ poly doping for CMOS circuits
TEXAS INSTRUMENTS INC9 citations83
US7537988B2May 26, 2009
Differential offset spacer
TEXAS INSTRUMENTS INC8 citations83
US7892930B2Feb 22, 2011
Method to improve transistor tox using SI recessing with no additional masking steps
TEXAS INSTRUMENTS INC2 citations62
US7812401B2Oct 12, 2010
MOS device and process having low resistance silicide interface using additional source/drain implant
TEXAS INSTRUMENTS INC3 citations62
US7727838B2Jun 1, 2010
Method to improve transistor Tox using high-angle implants with no additional masks
TEXAS INSTRUMENTS INC5 citations62
US7682892B2Mar 23, 2010
MOS device and process having low resistance silicide interface using additional source/drain implant
TEXAS INSTRUMENTS INC3 citations62
US7572716B2Aug 11, 2009
Semiconductor doping with improved activation
TEXAS INSTRUMENTS INC0 citations52
US8380476B2Feb 19, 2013
Modeling of ferroelectric capacitors to include local statistical variations of ferroelectric properties
TEXAS INSTRUMENTS INC0 citations41