Inventor
EKBOTE SHASHANK
US16 patents
⚠️ This page may combine multiple inventors who share the name “EKBOTE SHASHANK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TEXAS INSTRUMENTS INC
9 patentsUS6930007B2Aug 16, 2005
Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance
TEXAS INSTRUMENTS INC190 citations98
US7718482B2May 18, 2010
CD gate bias reduction and differential N+ poly doping for CMOS circuits
TEXAS INSTRUMENTS INC9 citations83
US7537988B2May 26, 2009
Differential offset spacer
TEXAS INSTRUMENTS INC8 citations83
US7812401B2Oct 12, 2010
MOS device and process having low resistance silicide interface using additional source/drain implant
TEXAS INSTRUMENTS INC3 citations62
US7682892B2Mar 23, 2010
MOS device and process having low resistance silicide interface using additional source/drain implant
TEXAS INSTRUMENTS INC3 citations62
US7601575B2Oct 13, 2009
Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance
TEXAS INSTRUMENTS INC2 citations62
US7897513B2Mar 1, 2011
Method for forming a metal silicide
TEXAS INSTRUMENTS INC5 citations61
US9947765B2Apr 17, 2018
Dummy gate placement methodology to enhance integrated circuit performance
TEXAS INSTRUMENTS INC0 citations50
US9496142B2Nov 15, 2016
Dummy gate placement methodology to enhance integrated circuit performance
TEXAS INSTRUMENTS INC0 citations50
QUALCOMM INC
6 patentsUS10861852B2Dec 8, 2020
Three-dimensional (3D), vertically-integrated field-effect transistors (FETs) for complementary metal-oxide semiconductor (CMOS) cell circuits
QUALCOMM INC10 citations84
US9634138B1Apr 25, 2017
Field-effect transistor (FET) devices employing adjacent asymmetric active gate / dummy gate width layout
QUALCOMM INC15 citations82
US10490558B2Nov 26, 2019
Reducing or avoiding mechanical stress in static random access memory (SRAM) strap cells
QUALCOMM INC4 citations72
US10062768B2Aug 28, 2018
Field-effect transistor (FET) devices employing adjacent asymmetric active gate / dummy gate width layout
QUALCOMM INC3 citations71
US9882051B1Jan 30, 2018
Fin field effect transistors (FETs) (FinFETs) employing dielectric material layers to apply stress to channel regions
QUALCOMM INC4 citations71
US10304957B2May 28, 2019
FinFET with reduced series total resistance
QUALCOMM INC1 citations59