Inventor
AYUB SALMA
US26 patents
Patents
26 patentsUS11144319B1Oct 12, 2021
Redistribution of architected states for a processor register file
IBM19 citations84
US9747217B2Aug 29, 2017
Distributed history buffer flush and restore handling in a parallel slice design
IBM3 citations73
US9740620B2Aug 22, 2017
Distributed history buffer flush and restore handling in a parallel slice design
IBM5 citations73
US10949213B2Mar 16, 2021
Logical register recovery within a processor
IBM2 citations72
US10133576B2Nov 20, 2018
Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries
IBM2 citations72
US12061909B2Aug 13, 2024
Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries
IBM0 citations62
US11941398B1Mar 26, 2024
Fast mapper restore for flush in processor
IBM1 citations62
US11734010B2Aug 22, 2023
Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries
IBM0 citations62
US11531548B1Dec 20, 2022
Fast perfect issue of dependent instructions in a distributed issue queue system
IBM1 citations62
US11150907B2Oct 19, 2021
Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries
IBM0 citations62
US10942745B2Mar 9, 2021
Fast multi-width instruction issue in parallel slice processor
IBM0 citations62
US10255071B2Apr 9, 2019
Method and apparatus for managing a speculative transaction in a processing unit
IBM1 citations62
US11360779B2Jun 14, 2022
Logical register recovery within a processor
IBM0 citations61
US12204902B2Jan 21, 2025
Routing instruction results to a register block of a subdivided register file based on register block utilization rate
IBM0 citations52
US11561794B2Jan 24, 2023
Evicting and restoring information using a single port of a logical register mapper and history buffer in a microprocessor comprising multiple main register file entries mapped to one accumulator register file entry
IBM0 citations52
US10248421B2Apr 2, 2019
Operation of a multi-slice processor with reduced flush and restore latency
IBM0 citations52
US10241790B2Mar 26, 2019
Operation of a multi-slice processor with reduced flush and restore latency
IBM0 citations52
US11188332B2Nov 30, 2021
System and handling of register data in processors
IBM0 citations51
US10649779B2May 12, 2020
Variable latency pipe for interleaving instruction tags in a microprocessor
IBM0 citations51
US10613868B2Apr 7, 2020
Variable latency pipe for interleaving instruction tags in a microprocessor
IBM0 citations51
US10120693B2Nov 6, 2018
Fast multi-width instruction issue in parallel slice processor
IBM1 citations51
US9996359B2Jun 12, 2018
Fast multi-width instruction issue in parallel slice processor
IBM0 citations51
US11068267B2Jul 20, 2021
High bandwidth logical register flush recovery
IBM0 citations49
US10740107B2Aug 11, 2020
Operation of a multi-slice processor implementing load-hit-store handling
IBM0 citations41
US10445100B2Oct 15, 2019
Broadcasting messages between execution slices for issued instructions indicating when execution results are ready
IBM0 citations41
US10831492B2Nov 10, 2020
Most favored branch issue
IBM0 citations39