Inventor
CHADHA SUNDEEP
US81 patents
Patents
50 patentsUS9367322B1Jun 14, 2016
Age based fast instruction issue
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Method for generating reusable behavioral code
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Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions
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Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions
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Utilizing programmable channels for allocation of buffer space and transaction control in data communications
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Data communication method and apparatus utilizing programmable channels for allocation of buffer space and transaction control
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Operation of a multi-slice processor preventing early dependent instruction wakeup
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Method and apparatus for implementing power-saving sleep mode in design with multiple clock domains
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Generating testcases based on numbers of testcases previously generated
IBM6 citations74
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Handling unaligned load operations in a multi-slice computer processor
IBM1 citations73
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Processor core including pre-issue load-hit-store (LHS) hazard prediction to reduce rejection of load instructions
IBM5 citations73
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Handling unaligned load operations in a multi-slice computer processor
IBM2 citations73
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Bypassing a higher level register file in a processor having a multi-level register file and a set of bypass registers
IBM2 citations73
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Distributed history buffer flush and restore handling in a parallel slice design
IBM3 citations73
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Distributed history buffer flush and restore handling in a parallel slice design
IBM5 citations73
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Efficient usage of a multi-level register file utilizing a register file bypass
IBM3 citations73
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Fusion to enhance early address generation of load instructions in a microprocessor
IBM4 citations72
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Linkable issue queue parallel execution slice processing method
IBM3 citations72
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Linkable issue queue parallel execution slice for a processor
IBM2 citations72
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Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries
IBM2 citations72
US9928128B2Mar 27, 2018
In-pipe error scrubbing within a processor core
IBM6 citations72
US9921833B2Mar 20, 2018
Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor
IBM3 citations72
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Speculative finish of instruction execution in a processor core
IBM4 citations72
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Age based fast instruction issue
IBM3 citations72
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Speculative finish of instruction execution in a processor core
IBM4 citations72
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Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor
IBM2 citations71
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Multi-slice processor issue of a dependent instruction in an issue queue based on issue of a producer instruction
IBM2 citations69
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Handling unaligned load operations in a multi-slice computer processor
IBM1 citations63
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Generating testcases based on numbers of testcases previously generated
IBM4 citations63
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Method, apparatus, and computer program product for optimizing packet flow control through buffer status forwarding
IBM2 citations63
US12061909B2Aug 13, 2024
Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries
IBM0 citations62
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Microprocessor that fuses load and compare instructions
IBM0 citations62
US11734010B2Aug 22, 2023
Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries
IBM0 citations62
US11150907B2Oct 19, 2021
Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries
IBM0 citations62
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Operation of a multi-slice processor implementing a hardware level transfer of an execution thread
IBM0 citations62
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Fast multi-width instruction issue in parallel slice processor
IBM0 citations62
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Handling unaligned load operations in a multi-slice computer processor
IBM0 citations62
US10719056B2Jul 21, 2020
Merging status and control data in a reservation station
IBM1 citations62
US10379867B2Aug 13, 2019
Asynchronous flush and restore of distributed history buffer
IBM1 citations62
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Mechanism for using a reservation station as a scratch register
IBM1 citations62
US7853420B2Dec 14, 2010
Performing temporal checking
IBM3 citations62
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Method and apparatus for performing temporal checking
IBM5 citations62
US10983797B2Apr 20, 2021
Program instruction scheduling
IBM0 citations52
US10909034B2Feb 2, 2021
Issue queue snooping for asynchronous flush and restore of distributed history buffer
IBM0 citations52
US10496406B2Dec 3, 2019
Handling unaligned load operations in a multi-slice computer processor
IBM0 citations52
US10318419B2Jun 11, 2019
Flush avoidance in a load store unit
IBM0 citations52
US10268518B2Apr 23, 2019
Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions
IBM0 citations52
US10255107B2Apr 9, 2019
Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions
IBM0 citations52
US10248421B2Apr 2, 2019
Operation of a multi-slice processor with reduced flush and restore latency
IBM0 citations52
US10241790B2Mar 26, 2019
Operation of a multi-slice processor with reduced flush and restore latency
IBM0 citations52
Showing the top 50 of 81 patents by PatentIndex Score.