Inventor
THOMPTO BRIAN WILLIAM
US27 patents
⚠️ This page may combine multiple inventors who share the name “THOMPTO BRIAN WILLIAM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
26 patentsUS9690586B2Jun 27, 2017
Processing of multiple instruction streams in a parallel slice processor
IBM26 citations94
US9690585B2Jun 27, 2017
Parallel slice processor with dynamic instruction stream mapping
IBM22 citations94
US9672043B2Jun 6, 2017
Processing of multiple instruction streams in a parallel slice processor
IBM29 citations94
US9665372B2May 30, 2017
Parallel slice processor with dynamic instruction stream mapping
IBM25 citations94
US7877580B2Jan 25, 2011
Branch lookahead prefetch for microprocessors
IBM41 citations92
US7421567B2Sep 2, 2008
Using a modified value GPR to enhance lookahead prefetch
IBM18 citations92
US9977678B2May 22, 2018
Reconfigurable parallel execution and load-store slice processor
IBM7 citations84
US9971602B2May 15, 2018
Reconfigurable processing method with modes controlling the partitioning of clusters and cache slices
IBM6 citations84
US7631308B2Dec 8, 2009
Thread priority method for ensuring processing fairness in simultaneous multi-threading microprocessors
IBM12 citations84
US7594096B2Sep 22, 2009
Load lookahead prefetch for microprocessors
IBM13 citations84
US7254700B2Aug 7, 2007
Fencing off instruction buffer until re-circulation of rejected preceding and branch instructions to avoid mispredict flush
IBM14 citations84
US7254697B2Aug 7, 2007
Method and apparatus for dynamic modification of microprocessor instruction group at dispatch
IBM18 citations83
US10983800B2Apr 20, 2021
Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slices
IBM2 citations73
US10157064B2Dec 18, 2018
Processing of multiple instruction streams in a parallel slice processor
IBM2 citations73
US10083039B2Sep 25, 2018
Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slices
IBM3 citations73
US7444498B2Oct 28, 2008
Load lookahead prefetch for microprocessors
IBM6 citations73
US10223125B2Mar 5, 2019
Linkable issue queue parallel execution slice processing method
IBM3 citations72
US10133576B2Nov 20, 2018
Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries
IBM2 citations72
US10133581B2Nov 20, 2018
Linkable issue queue parallel execution slice for a processor
IBM2 citations72
US12061909B2Aug 13, 2024
Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries
IBM0 citations62
US11734010B2Aug 22, 2023
Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries
IBM0 citations62
US11150907B2Oct 19, 2021
Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries
IBM0 citations62
US7620799B2Nov 17, 2009
Using a modified value GPR to enhance lookahead prefetch
IBM2 citations62
US7552318B2Jun 23, 2009
Branch lookahead prefetch for microprocessors
IBM3 citations62
US7478276B2Jan 13, 2009
Method for checkpointing instruction groups with out-of-order floating point instructions in a multi-threaded processor
IBM4 citations62
US7650486B2Jan 19, 2010
Dynamic recalculation of resource vector at issue queue for steering of dependent instructions
IBM0 citations52