Inventor

CHUDZIK MICHAEL P

US116 patents

⚠️ This page may combine multiple inventors who share the name “CHUDZIK MICHAEL P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHUDZIK MICHAEL P

IBM

Sige channel epitaxial development for high-k PFET manufacturability

Method for forming a uniform distribution of nitrogen in silicon oxynitride gate dielectric

Structure and method for replacement gate MOSFET with self-aligned contact using sacrificial mandrel dielectric

Semiconductor device having dual metal gates and method of manufacture

Deep trench (DT) metal-insulator-metal (MIM) capacitor

Integration scheme for multiple metal gate work function structures

Stabilization of flatband voltages and threshold voltages in hafnium oxide based silicon transistors for CMOS

High density MIMCAP with a unit repeatable structure

Method of providing threshold voltage adjustment through gate dielectric stack modification

Fabrication of a CMOS structure with a high-k dielectric layer oxidizing an aluminum layer in PFET region

Introduction of metal impurity to change workfunction of conductive electrodes

Dual metal gate self-aligned integration

Method of forming an ultra-thin [[HfSiO]] metal silicate film for high performance CMOS applications and semiconductor structure formed in said method

Semiconductor method and structure for simultaneously forming a trench capacitor dielectric and trench sidewall device dielectric

Process flow for capacitance enhancement in a DRAM trench

Germanium oxide free atomic layer deposition of silicon oxide and high-k gate dielectric on germanium containing channel for CMOS devices

High performance CMOS circuits, and methods for fabricating same

Self-aligned CMOS structure with dual workfunction

High-k dielectric and metal gate stack with minimal overlap with isolation region and related methods

Gate effective-workfunction modification for CMOS

Dual metal gate self-aligned integration

Direct contact between high-κ/metal gate and wiring process flow

Method for tuning the threshold voltage of a metal gate and high-k device

Metal gates with low charge trapping and enhanced dielectric reliability characteristics for high-k gate dielectric stacks

Introduction of metal impurity to change workfunction of conductive electrodes

PFET with tailored dielectric and related methods and integrated circuit

Dual metal and dual dielectric integration for metal high-k FETs

Method of manufacturing high dielectric constant material

Hydroxyl group termination for nucleation of a dielectric metallic oxide

GLOBALFOUNDRIES INC

Merged source drain epitaxy

FinFET and nanowire semiconductor devices with suspended channel regions and gate structures surrounding the suspended channel regions

Integrated circuit having improved electromigration performance and method of forming same

Replacement channel TFET

Replacement metal gate structures for effective work function control

CHUDZIK MICHAEL P

Method and structure for gate height scaling with high-k/metal gate technology

Method and structure for gate height scaling with high-k/metal gate technology

Thermally stable high-K tetragonal HFO2 layer within high aspect ratio deep trenches

LI ZHENGWEN

Structure and method to make replacement metal gate and contact metal

Etch stop layer formation in metal gate process

Self-aligned bottom plate for metal high-K dielectric metal insulator metal (MIM) embedded dynamic random access memory

ANDO TAKASHI

Replacement gate with reduced gate leakage current

Replacement gate devices with barrier metal for simultaneous processing

UNIV CHICAGO

Method for preparing high temperature superconductor

KWON UNOH

Replacement metal gate structures for effective work function control

BEDELL STEPHEN W

Method and structure for PMOS devices with high K metal gate integration and SiGe channel engineering

INFINEON TECHNOLOGIES CORP

Silicon nitride island formation for increased capacitance

KIM BYEONG Y

Thermal dual gate oxide device integration

GREENE BRIAN J

Threshold voltage adjustment through gate dielectric stack modification

BREIL NICOLAS

Non-volatile memory structure employing high-k gate dielectric and metal gate

ADAMS CHARLOTTE DEWAN

Semiconductor devices having different gate oxide thicknesses