Inventor

DIVAKARUNI RAMACHANDRA

US252 patents

⚠️ This page may combine multiple inventors who share the name “DIVAKARUNI RAMACHANDRA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DIVAKARUNI RAMACHANDRA

IBM

Vertical Fin-FET MOS devices

Process for fabrication of FinFETs

Semiconductor device of an embedded DRAM on SOI substrate

Method for hybrid DRAM cell utilizing confined strap isolation

Embedded DRAM on silicon-on-insulator substrate

Trench optical device

Method for making multiple threshold voltage FET using multiple work-function gate materials

Method for novel SOI DRAM BICMOS NPN

Vertical trench-formed dual-gate FET device structure and method for creation

Method of manufacturing 6F2 trench capacitor DRAM cell having vertical MOSFET and 3F bitline pitch

Deep slit isolation with controlled void

Vertical MOSFET

Structure and method of fabricating embedded vertical DRAM arrays with silicided bitline and polysilicon interconnect

Single sided buried strap

Structures and methods of anti-fuse formation in SOI

Structure and process for 6F2 trench capacitor DRAM cell with vertical MOSFET and 3F bitline pitch

Double polysilicon process for providing single chip high performance logic and compact embedded memory structure

Method for providing dual work function doping and protective insulating cap

Embedded vertical DRAM cells and dual workfunction logic gates

Shallow trench isolation method utilizing combination of spacer and fill

Stacked nanowire devices

Integrated strained stacked nanosheet FET

FinFET CMOS with Si NFET and SiGe PFET

Method and structure for forming a localized SOI finFET

Strained finFET with an electrically isolated channel

Vertical metal-insulator-metal (MIM) capacitor using gate stack, gate spacer and contact via

Dual port gain cell with side and top gated read transistor

Integration scheme for multiple metal gate work function structures

Patterned strained semiconductor substrate and device

Buried plate structure for vertical dram devices

Dual port gain cell with side and top gated read transistor

Method of creating deep trench capacitor using a P+ metal electrode

Patterned strained semiconductor substrate and device

Method of forming connection and anti-fuse in layered substrate such as SOI

Process for forming a buried plate

Trench capacitor DRAM cell using buried oxide as array top oxide

Low-cost deep trench decoupling capacitor device and process of manufacture

SOI device with different crystallographic orientations

Out of the box vertical transistor for eDRAM on SOI

Deep trench capacitor with buried plate electrode and isolation collar

Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI structure with elevated source/drain

Out of the box vertical transistor for eDRAM on SOI

Method for forming buried plate of trench capacitor

Method of creating deep trench capacitor using a P+ metal electrode

Vertical DRAM punchthrough stop self-aligned to storage trench

Trench capacitor DRAM cell using buried oxide as array top oxide

Vertical DRAM punchthrough stop self-aligned to storage trench

Memory cell with vertical transistor and trench capacitor with reduced burried strap

Method of fabricating a patterened SOI embedded DRAM/eDRAM having a vertical device cell and device formed thereby

INFINEON TECHNOLOGIES CORP

Single sided buried strap