Inventor

YANG HAINING S

US139 patents

⚠️ This page may combine multiple inventors who share the name “YANG HAINING S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YANG HAINING S

IBM

Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions

Strained silicon NMOS devices with embedded source/drain

Sub-lithographic interconnect patterning using self-assembling polymers

FinFET with sublithographic fin width

Reversible electric fuse and antifuse structures for semiconductor devices

Metal silicide alloy local interconnect

MOSFET structure with high mechanical stress in the channel

Complementary transistors having different source and drain extension spacing controlled by different spacer sizes

Structure and method of making strained channel CMOS transistors having lattice-mismatched epitaxial extension and source and drain regions

Hybrid interconnect structure for performance improvement and reliability enhancement

Electrical fuse and method of making

Device patterned with sub-lithographic features with variable widths

FinFET SRAM with asymmetric gate and method of manufacture thereof

Integration scheme for multiple metal gate work function structures

Dual damascene metal interconnect structure having a self-aligned via

Semiconductor device structure having enhanced performance FET device

Two-sided semiconductor-on-insulator structures and methods of manufacturing the same

Dual stress liner

Method and apparatus to increase strain effect in a transistor channel

Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions

Structure for strained channel field effect transistor pair having a member and a contact via

Structure and method to improve SRAM stability without increasing cell area or off current

Hybrid interconnect structure for performance improvement and reliability enhancement

Method for reducing tip-to-tip spacing between lines

Carrier mobility enhanced channel devices and method of manufacture

Structure and method to integrate dual silicide with dual stress liner to improve CMOS performance

Heterojunction tunneling field effect transistors, and methods for fabricating the same

Partially gated FINFET with gate dielectric on only one sidewall

Methods and systems involving electrically programmable fuses

Electrical fuse having sublithographic cavities thereupon

Non-planar fuse structure including angular bend

Electrical fuses and resistors having sublithographic dimensions

Method to increase strain enhancement with spacerless FET and dual liner process

SOI substrates and SOI devices, and methods for forming the same

Structure and method to form improved isolation in a semiconductor device

High performance 3D FET structures, and methods for forming the same using preferential crystallographic etching

High performance 3D FET structures, and methods for forming the same using preferential crystallographic etching

CMOS gate conductor having cross-diffusion barrier

Methods for forming CMOS devices with intrinsically stressed metal silicide layers

Electrical fuse and method of making

Multiwalled carbon nanotube memory device

High performance MOSFET comprising a stressed gate metal silicide layer and method of fabricating the same

Process for making FinFET device with body contact and buried oxide junction isolation

Structure and method to optimize strain in CMOSFETs

CHEN XIANGDONG

Heterojunction tunneling field effect transistors, and methods for fabricating the same

Heterojunction tunneling field effect transistors, and methods for fabricating the same

LI WAI-KIN

Patterning method using a combination of photolithography and copolymer self-assemblying lithography techniques

HEYMANN OMER

Boost cell supply write assist

DYER THOMAS W

Semiconductor devices having tensile and/or compressive stress and methods of manufacturing

CHENG KANGGUO

Replacement gate CMOS