Inventor

JEDDELOH JOSEPH M

US190 patents

⚠️ This page may combine multiple inventors who share the name “JEDDELOH JOSEPH M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JEDDELOH JOSEPH M

MICRON TECHNOLOGY INC

Memory system and method using stacked memory device dice, and system using the memory system

Memory hub and method for memory system performance monitoring

System and method for on-board diagnostics of memory modules

Memory hub with internal cache and/or memory access prediction

Reconfigurable memory module and method

Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules

Method and system for controlling memory accesses to memory modules having a memory hub architecture

System and method for self-testing and repair of memory modules

Method of timing calibration using slower data rate pattern

Timing circuit for high speed memory

Method for aligning clock and data signals received from a RAM

Apparatus for aligning clock and data signals received from a RAM

System and method for selective memory module power management

System and method for selective memory module power management

System and method for memory hub-based expansion bus

Buffer control system and method for a memory system having outstanding read and write request buffers

Memory hub and method for memory sequencing

Multiple processor system and method including multiple memory hub modules

Memory hub bypass circuit and method

Storing a flushed cache line in a memory buffer of a controller

Method for synchronizing strobe and data signals from a RAM

Method for aligning clock and data signals received from a RAM

Memory bandwidth allocation based on access count priority scheme

Apparatus for aligning clock and data signals received from a RAM

Memory system and method using stacked memory device dice, and system using the memory system

Multiple processor system and method including multiple memory hub modules

System and method for memory hub-based expansion bus

System and method for memory hub-based expansion bus

Wavelength division multiplexed memory module, memory system and method

Apparatus for synchronizing strobe and data signals received from a RAM

Controlling a paging policy based on a requestor characteristic

Method for providing additional latency for synchronously accessed memory

Memory system and method using stacked memory device dice, and system using the memory system

Method and apparatus for testing high capacity/high bandwidth memory devices

System and method for memory hub-based expansion bus

Multiple processor system and method including multiple memory hub modules

Memory hub and method for providing memory sequencing hints

System and method for arbitration of memory responses in a hub-based memory system

Memory hub and access method having internal prefetch buffers

Reconfigurable memory module and method

System and method for on-board timing margin testing of memory modules

Memory hub tester interface and method for use thereof

MICRON ELECTRONICS INC

Apparatus for providing additional latency for synchronously accessed memory

Memory controller with low skew control signal

Apparatus for providing additional latency for synchronously accessed memory

Method for aligning a control signal and a clock signal

Memory controller with low skew control signal

JEDDELOH JOSEPH M

Devices and methods for operating a solid state drive

Multi-mode memory device and method having stacked memory dice, a logic die and a command processing circuit and operating in direct and indirect modes

Stripe based memory operation