Inventor

SONG SEUNGYOON PETER

US34 patents

⚠️ This page may combine multiple inventors who share the name “SONG SEUNGYOON PETER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SONG SEUNGYOON PETER

SUN MICROSYSTEMS INC

Adaptive computing ensemble microprocessor architecture

Prefetch hardware efficiency via prefetch hint instructions

Software hint to specify the preferred branch prediction to use for a branch instruction

Flag management in processors enabled for speculative execution of micro-operation traces

Power conservation via DRAM access reduction

Small and power-efficient cache that can provide data for background DNA devices while the processor is in a low-power state

Reducing power consumption for processing of common values in microprocessor registers and execution units

Flag management in processors enabled for speculative execution of micro-operation traces

Flag management in processors enabled for speculative execution of micro-operation traces

ORACLE AMERICA INC

Power conservation via DRAM access

Virtual core management

Virtual core management

Prediction of data values read from memory by a microprocessor using the storage destination of a load operation

Small and power-efficient cache that can provide data for background DMA devices while the processor is in a low-power state

Power conservation via DRAM access reduction

SAMSUNG ELECTRONICS CO LTD

Scalable width vector processor architecture for efficient emulation

Single-instruction-multiple-data processing using multiple banks of vector registers

Deferred store data read with simple anti-dependency pipeline inter-lock control in superscalar processor

Multifunction data aligner in wide data width processor

CHENG YU QING

Virtual core management

Virtual core management

Virtual core remapping based on temperature

Virtual core management

IBM

Method and system for efficiently mapping guest instruction in an emulation assist unit

Predictive translation of a data address utilizing sets of associative entries stored consecutively in a translation lookaside buffer

Processing system and method of operation for concurrent processing of branch instructions with cancelling of processing of a branch instruction

Method and system for reordering instructions after dispatch in a processing system

MOTOROLA INC

Data processor with branch target address cache and method of operation

Data processor with branch prediction and method of operation

Data processor with an execution unit for performing load instructions and method of operation

ELAN RES INC

Operand file using pointers and reference counters and a method of use

Method and system for programmable replacement mechanism for caching devices

SAMSUNG ELECTRONICS INC

Efficient context saving and restoring in a multi-tasking computing system environment

PICOTURBO INC

Method and system for selective DRAM refresh to reduce power consumption