Inventor

BAL ANKUR

IN67 patents

⚠️ This page may combine multiple inventors who share the name “BAL ANKUR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BAL ANKUR

ST MICROELECTRONICS INT NV

Self-calibrated digital-to-analog converter

High speed data weighted averaging architecture

Apparatus for built-in self-test (BIST) of a Nyquist rate analog-to-digital converter (ADC) circuit

Timing skew mismatch calibration for time interleaved analog to digital converters

Timing skew mismatch calibration for time interleaved analog to digital converters

On chip test architecture for continuous time delta sigma analog-to-digital converter

Sigma-delta analog-to-digital converter circuit with real time correction for digital-to-analog converter mismatch error

High throughput parallel architecture for recursive sinusoid synthesizer

Sigma-delta analog-to-digital converter circuit with correction for mismatch error introduced by the feedback digital-to-analog converter

Clock jitter measurement using signal-to-noise ratio degradation in a continuous time delta-sigma modulator

High speed data weighted averaging architecture

High speed data weighted averaging architecture

Methods, systems, and apparatuses for reducing DC bias

Low overhead loop back test for high speed transmitter

On chip test architecture for continuous time delta sigma analog-to-digital converter

Low overhead mesochronous digital interface

High throughput digital filter architecture for processing unary coded data

High throughput parallel architecture for recursive sinusoid synthesizer

Data bridge for interfacing source synchronous datapaths with unknown clock phases

Low power and high speed data weighted averaging (DWA) to binary converter circuit

Phase-independent testing of a converter

Sigma-delta analog-to-digital converter circuit with real time correction for digital-to-analog converter mismatch error

High frequency resolution digital sinusoid generator

High speed data weighted averaging (DWA) to binary converter circuit

Digital sinusoid generator

Device and method for time skew calibration of multi channel ADC

Method and circuit for calibration of high-speed data interface

First order memory-less dynamic element matching technique

First order memory-less dynamic element matching technique

Programmable delay circuit

Noise removal system

Clock phase noise measurement circuit and method

Method and device for testing successive approximation register analog-to-digital converters

Device with low-power synchronizing circuitry and related method

Debounce circuit with noise immunity and glitch event tracking

Sigma-delta analog-to-digital converter circuit with data sharing for power saving

SGS THOMSON MICROELECTRONICS

System for simplifying the programmable memory to logic interface in FPGA

Programmable logic device including bi-directional shift register

Method for sharing configuration data for high logic density on chip

System for rapid configuration of a programmable logic device

Concurrent logic operations using decoder circuitry of a look-up table

BAL ANKUR

Filter block for compensating droop in a frequency response of a signal

Apparatus for signal processing

Signal synchronizing systems and methods

Noise removal system

ST MICROELECTRONICS PVT LTD

Methods and apparatus for offline mismatch removal in sigma delta analog-to-digital converters

FPGA peripheral routing with symmetric edge termination at FPGA boundaries

High performance interconnect architecture for field programmable gate arrays

PARIDA RAKHEL KUMAR

Glitch free dynamic element matching scheme

SINGH VIKRAM

DC-AC converter