Inventor

TSERN ELY K

US154 patents

⚠️ This page may combine multiple inventors who share the name “TSERN ELY K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TSERN ELY K

RAMBUS INC

Method and apparatus for signaling between devices of a memory system

Low power memory device

System for a memory device having a power down mode and method

Method and apparatus for signaling between devices of a memory system

Memory controller with power management logic

Method and apparatus for configuring access times of memory devices

Power control system for synchronous memory device

Method and apparatus for coordinating memory operations among diversely-located memory components

DRAM core refresh with reduced spike current

Power control system for synchronous memory device

Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain

Dram core refresh with reduced spike current

Memory system with error detection and retry modes of operation

Memory with refresh cycle donation to accommodate low-retention-storage rows

Memory device testing to support address-differentiated refresh rates

Timing calibration apparatus and method for a memory device signaling system

Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules

Apparatus and method for generating a distributed clock signal using gear ratio techniques

Apparatus and method for thermal regulation in memory subsystems

Apparatus and method for thermal regulation in memory subsystems

Method and apparatus for coordinating memory operations among diversely-located memory components

Method, system and memory controller utilizing adjustable write data delay settings

Memory device with clock multiplier circuit

Method, system and memory controller utilizing adjustable read data delay settings

Memory module with offset data lines and bit line swizzle configuration

Memory system with channel multiplexing of multiple memory devices

DRAM core refresh with reduced spike current

DRAM core refresh with reduced spike current

Memory module

Memory component with terminated and unterminated signaling inputs

Upgradable memory system with reconfigurable interconnect

Power control system for synchronous memory device

Memory module with termination component

Memory module with termination component

Apparatus and method for generating a distributed clock signal using gear ratio techniques

Asynchronous, high-bandwidth memory component using calibrated timing elements

Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules

Expandable slave device system

Synchronous memory device having a temperature register

Method and apparatus for adjusting the performance of a synchronous memory system

High speed memory system capable of selectively operating in non-chip-kill and chip-kill modes

Apparatus and method for pipelined memory operations

Apparatus and method for bus timing compensation

Phase adjustment apparatus and method for a memory device signaling system

High capacity memory systems with inter-rank skew tolerance

WARE FREDERICK A

Memory controller with selective data transmission delay

Memory module with termination component

Memory controller device having timing offset capability

INTEL CORP

Memory device and system including a low power interface

BEST SCOTT C

Memory controller with refresh logic to accommodate low-retention storage rows in a memory device