Inventor

SHIRAIWA HIDEHIKO

US74 patents

⚠️ This page may combine multiple inventors who share the name “SHIRAIWA HIDEHIKO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHIRAIWA HIDEHIKO

ADVANCED MICRO DEVICES INC

Flash memory erase speed by fluorine implant or fluorination

Process for reducing hydrogen contamination in dielectric materials in memory devices

Semiconductor memory with deuterated materials

Planar structure for non-volatile memory devices

Method of simultaneous formation of bitline isolation and periphery oxide

Source drain implant during ONO formation for improved isolation of SONOS devices

Trench side wall charge trapping dielectric flash memory device

Simultaneous formation of charge storage and bitline to wordline isolation

Simultaneous formation of charge storage and bitline to wordline isolation

Charge-trapping memory arrays resistant to damage from contact hole information

Structure and method for preventing UV radiation damage and increasing data retention in memory cells

Memory manufacturing process using bitline rapid thermal anneal

Method of making memory wordline hard mask extension

Method of forming ONO flash memory devices using low energy nitrogen implantation

Alignment system for planar charge trapping dielectric memory cell lithography

Method of forming ONO flash memory devices using rapid thermal oxidation

Memory manufacturing process using disposable ARC for wordline formation

Hard mask process for memory device without bitline shorts

SPANSION LLC

Memory cell having enhanced high-K dielectric

Integrated ONO processing for semiconductor devices using in-situ steam generation (ISSG) process

SONOS memory with inversion bit-lines

Method of formation of gate stack spacer and charge storage materials having reduced hydrogen content in charge trapping dielectric flash memory device

Non-volatile memory with silicided bit line contacts

Non-Volatile memory with silicided bit line contacts

Methods for fabricating flash memory devices

Aluminum oxide as liner or cover layer to spacers in memory device

One stack with steam oxide for charge retention

Structure and method for preventing UV radiation damage in a memory cell and improving contact CD control

High K stack for non-volatile memory

Self-aligned STI SONOS

Multiple dual bit memory integrated circuit system

SONOS memory with inversion bit-lines

Semiconductor device and method for controlling operation thereof

Semiconductor memory with data retention liner

FASL LLC

Memory device having high work function gate and method of erasing same

ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices

ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices

Recessed channel with separated ONO memory device

Process for fabrication of nitride layer with reduced hydrogen content in ONO structure in semiconductor device

ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices

Flash memory device and method of fabrication thereof including a bottom oxide layer with two regions with different concentrations of nitrogen

Process for fabrication of spacer layer with reduced hydrogen content in semiconductor device

Method of manufacturing a semiconductor memory with deuterated materials

Dummy wordline for erase and bitline leakage

Liner for semiconductor memories and manufacturing method therefor

Recessed channel with separated ONO memory device

LIN CHUAN

Integrating transistors with different poly-silicon heights on the same die

FUJITSU LTD

Method for fabricating semiconductor devices that prevents pattern contamination

CHAN SIMON SIU-SING

Method and manufacture for embedded flash to achieve high quality spacers for core and high voltage devices and low temperature spacers for high performance logic devices

ROY ALOK NANDINI

Shallow bipolar junction transistor