Inventor

MAHALINGAIAH RUPAKA

US62 patents

⚠️ This page may combine multiple inventors who share the name “MAHALINGAIAH RUPAKA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MAHALINGAIAH RUPAKA

ADVANCED MICRO DEVICES INC

Superscalar microprocessor configured to predict return addresses from a return stack storage

Superscalar microprocessor configured to predict return addresses from a return stack storage

Apparatus and method for microcode patching for generating a next address

Speculative store buffer

Apparatus and method for tracing microprocessor instructions

Superscalar microprocessor configured to predict return addresses from a return stack storage

Apparatus and method for patching an instruction by providing a substitute instruction or instructions from an external memory responsive to detecting an opcode of the instruction

Apparatus and method for tracing microprocessor instructions

Context-dependent memory-mapped registers for transparent expansion of a register file

Speculative register file for storing speculative register states and removing dependencies between instructions utilizing the register

Interrupt transmission via specialized bus cycle within a symmetrical multiprocessing system

Apparatus for detecting updates to instructions which are within an instruction processing pipeline of a microprocessor

Interrupt handling mechanism to prevent spurious interrupts in a symmetrical multiprocessing system

Interrupt control architecture for symmetrical multiprocessing system

Heuristic clock speed optimizing mechanism and computer system employing the same

Using separate caches for variable and generated fixed-length instructions

Microprocessor configured to detect updates to instructions outstanding within an instruction processing pipeline and computer system including same

Forcing regularity into a CISC instruction set by padding instructions

Method and system using tagged instructions to allow out-of-program-order instruction decoding

Using ECC/parity bits to store predecode information

Method for detecting updates to instructions which are within an instruction processing pipeline of a microprocessor

Apparatus and method for predicting an end of a microcode loop

Apparatus for efficiently providing memory operands for instructions

Speculative register storage for storing speculative results corresponding to register updated by a plurality of concurrently recorded instruction

Apparatus and method for predicting an end of loop for string instructions

Return address prediction system which adjusts the contents of return stack storage to enable continued prediction after a mispredicted branch

Workload balancing in a microprocessor for reduced instruction dispatch stalling

Apparatus for providing memory and register operands concurrently to functional units

Conditional early data address generation mechanism for a microprocessor

Apparatus and method for detecting microbranches early

Apparatus and method for floating point exchange dispatch with reduced latency

Pairing floating point exchange instruction with another floating point instruction to reduce dispatch latency

Determining microcode entry points and prefix bytes using a parallel logic technique

Interrupt cascading and priority configuration for a symmetrical multiprocessing system

Reduced size storage apparatus for storing cache-line-related data in a high frequency microprocessor

Predecoding multiple instructions as one combined instruction and detecting branch to one of the instructions

DUNTI LLC

Apparatus, system, and method for routing data to and from a host that is moved from one location on a communication system to another location on the communication system

Communication network having packetized security codes and a system for detecting security breach locations within the network

Communication network and protocol which can efficiently maintain transmission across a disrupted network

Network packet transmission mechanism

Communication network having modular switches that enhance data throughput

Address mapping mechanism enabling multi-domain addressing in communication networks

MAHALINGAIAH RUPAKA

Method and apparatus for securing communication over public network

Method and apparatus for enabling mobile cluster computing

Method and apparatus for providing continuous user verification in a packet-based network

DUNTI CORP

Communication network across which packets of data are transmitted according to a priority scheme

Address mapping mechanism enabling multi-domain addressing in communication networks

Modular switches interconnected across a communication network to achieve minimal address mapping or translation between termination devices

(unassigned)

Method and apparatus for generation and synchronization of distributed pulse clocked mechanism digital designs

Method and apparatus for executing plurality of operations per clock cycle in a single processing unit with a self-timed and self-enabled distributed clock