Inventor

SIDIROPOULOS STEFANOS

US92 patents

⚠️ This page may combine multiple inventors who share the name “SIDIROPOULOS STEFANOS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SIDIROPOULOS STEFANOS

RAMBUS INC

Calibrated data communication system and method

Low latency multi-level communication interface

Calibrated data communication system and method

System featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices

System featuring memory modules that include an integrated circuit buffer devices

System and method featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices

Integrated circuit with timing adjustment mechanism and method

Clock alignment circuit having a self regulating voltage supply

Apparatus and method for controlling a master/slave system via master device synchronization

Bus system optimization

Memory system including a point-to-point linked memory subsystem

Apparatus and method for generating multiple clock signals from a single loop circuit

Variable delay element

Slave device with synchronous interface for use in synchronous memory system

Method and apparatus for calibrating a multi-level current mode driver having a plurality of source calibration signals

Method and apparatus for calibrating a multi-level current mode driver having a plurality of source calibration signals

Method and apparatus for calibrating a multi-level current mode driver

Low latency multi-level communication interface

System having a controller device, a buffer device and a plurality of memory devices

System featuring a master device, a buffer device and a plurality of integrated circuit memory devices

Synchronous memory device having a temperature register

Method and apparatus for adjusting the performance of a synchronous memory system

Apparatus and method for edge based duty cycle conversion

Dual loop phase lock loops using dual voltage supply regulators

Apparatus and method for controlling a master/slave system via master device synchronization

Apparatus and method for controlling a master/slave system via master device synchronization

Integrated circuit buffer device

Memory module having an integrated circuit buffer device

Buffer device and method of operation in a buffer device

Reducing coupled noise in pseudo-differential signaling systems

Integrated circuit buffer device

Integrated circuit buffer device

System and method for aligning internal transmit and receive clocks

Duty cycle integrator with tracking common mode feedback control

Apparatus and method for edge based duty cycle conversion

Multi-PAM output driver with distortion compensation

Memory controller that calibrates a transmit timing offset

Multiphase receiver with equalization

Dual loop phase lock loops using dual voltage supply regulators

Memory component with pattern register circuitry to provide data patterns for calibration

Memory component with pattern register circuitry to provide data patterns for calibration

NETLOGIC MICROSYSTEMS INC

Methods and apparatus for generating multiple clocks using feedback interpolation

Methods and apparatus to increase the resolution of a clock synthesis circuit that uses feedback interpolation

Methods and apparatus for frequency synthesis with feedback interpolation

ZERBE JARED L

Integrating receiver with precharge circuitry

Multiphase receiver with equalization circuitry

NET LOGIC MICROSYSTEMS INC

Methods and apparatus for clock and data recovery using a single source

Methods and apparatus for minimizing jitter in a clock synthesis circuit that uses feedback interpolation

ZERBE JARED LEVAN

Memory system with calibrated data communication

NEXLOGIC MICROSYSTEMS INC

Programmable delay clock buffer