Inventor
KEPPEL DAVID
US36 patents
⚠️ This page may combine multiple inventors who share the name “KEPPEL DAVID”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
16 patentsUS9116729B2Aug 25, 2015
Handling of binary translated self modifying code and cross modifying code
INTEL CORP10 citations80
US10135708B2Nov 20, 2018
Technologies for performance inspection at an endpoint node
INTEL CORP4 citations72
US10409763B2Sep 10, 2019
Apparatus and method for efficiently implementing a processor pipeline
INTEL CORP6 citations70
US9442849B2Sep 13, 2016
Apparatus and method for reduced core entry into a power state having a powered down core cache
INTEL CORP2 citations61
US12438960B2Oct 7, 2025
Metadata compaction in packet coalescing
INTEL CORP0 citations59
US11989135B2May 21, 2024
Programmable address range engine for larger region sizes
INTEL CORP0 citations55
US12405727B2Sep 2, 2025
Method and apparatus for data buffering of write operations and performing write operations
INTEL CORP0 citations53
US12242753B2Mar 4, 2025
Reduced network load with combined put or get and receiver-managed offset
INTEL CORP0 citations53
US10771404B2Sep 8, 2020
Performance monitoring
INTEL CORP0 citations52
US10061376B2Aug 28, 2018
Opportunistic power management for managing intermittent power available to data processing device having semi-non-volatile memory or non-volatile memory
INTEL CORP1 citations52
US9766685B2Sep 19, 2017
Controlling power consumption of a processor using interrupt-mediated on-off keying
INTEL CORP1 citations52
US10135711B2Nov 20, 2018
Technologies for sideband performance tracing of network traffic
INTEL CORP1 citations51
US9965023B2May 8, 2018
Apparatus and method for flushing dirty cache lines based on cache activity levels
INTEL CORP0 citations51
US10331550B2Jun 25, 2019
Symmetric addressing
INTEL CORP0 citations42
US10178041B2Jan 8, 2019
Technologies for aggregation-based message synchronization
INTEL CORP0 citations41
US10200310B2Feb 5, 2019
Fabric-integrated data pulling engine
INTEL CORP0 citations36
TRANSMETA CORP
10 patentsUS6738892B1May 18, 2004
Use of enable bits to control execution of selected instructions
TRANSMETA CORP106 citations98
US5905855AMay 18, 1999
Method and apparatus for correcting errors in computer systems
TRANSMETA CORP140 citations97
US6356615B1Mar 12, 2002
Programmable event counter system
TRANSMETA CORP57 citations96
US6415379B1Jul 2, 2002
Method and apparatus for maintaining context while executing translated instructions
TRANSMETA CORP57 citations95
US6363336B1Mar 26, 2002
Fine grain translation discrimination
TRANSMETA CORP63 citations94
US6714904B1Mar 30, 2004
System for using rate of exception event generation during execution of translated instructions to control optimization of the translated instructions
TRANSMETA CORP33 citations92
US6668287B1Dec 23, 2003
Software direct memory access
TRANSMETA CORP39 citations91
US6845353B1Jan 18, 2005
Interpage prologue to protect virtual address mappings
TRANSMETA CORP15 citations83
US6513110B1Jan 28, 2003
Check instruction and method
TRANSMETA CORP17 citations82
US6829719B2Dec 7, 2004
Method and apparatus for handling nested faults
TRANSMETA CORP6 citations74
SHERWOOD SERV AG
3 patentsUS7137980B2Nov 21, 2006
Method and system for controlling output of RF medical generator
SHERWOOD SERV AG2,296 citations99
US6203541B1Mar 20, 2001
Automatic activation of electrosurgical generator bipolar output
SHERWOOD SERV AG342 citations99
US6402741B1Jun 11, 2002
Current and status monitor
SHERWOOD SERV AG158 citations95
BEDICHEK ROBERT
3 patentsUS7761857B1Jul 20, 2010
Method for switching between interpretation and dynamic translation in a processor system based upon code sequence execution counts
BEDICHEK ROBERT11 citations82
US8418153B2Apr 9, 2013
Method for integration of interpretation and translation in a microprocessor
BEDICHEK ROBERT0 citations50
US7617088B1Nov 10, 2009
Interpage prologue to protect virtual address mappings
BEDICHEK ROBERT1 citations50