Inventor

ROZARIO RANJIT J

US20 patents

⚠️ This page may combine multiple inventors who share the name “ROZARIO RANJIT J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ROZARIO RANJIT J

MIPS TECH LLC

Hardware virtualized input output memory management unit

Virtualized-in-hardware input output memory management

Virtualized-in-hardware Input Output Memory Management

Virtualized-in-hardware input output memory management

Processors supporting atomic writes to multiword memory locations and methods

Translation lookaside buffer

Modeless instruction execution with 64/32-bit addressing

IMAGINATION TECH LTD

Translation lookaside buffer

Crossing pipelined data between circuitry in different clock domains

Crossing pipelined data between circuitry in different clock domains

Processors and methods for cache sparing stores

Pipelined ECC-protected memory access

ADVANCED MICRO DEVICES INC

Method for ordering a request for access to a system memory using a reordering buffer or FIFO

Gear box for multiple clock domains

Arbitrating FIFO implementation which positions input request in a buffer according to its status

REDBACK NETWORKS INC

Free memory manager scheme and cache

Scheduler for a direct memory access device having multiple channels

Free memory manager scheme and cache

(unassigned)

Computer system including system controller with a write buffer and plural read buffers for decoupled busses

CHEN EDMUND G

Digital counter segmented into short and long access time memory