Inventor

DEBNATH KATHAKALI

US2 patents

Patents

2 patents

US5666537ASep 9, 1997

Power down scheme for idle processor components

INTEL CORP133 citations92

US5630107AMay 13, 1997

System for loading PLL from bus fraction register when bus fraction register is in either first or second state and bus unit not busy

INTEL CORP54 citations90