Inventor
SINGH DESHANAND
CA48 patents
⚠️ This page may combine multiple inventors who share the name “SINGH DESHANAND”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ALTERA CORP
35 patentsUS7107477B1Sep 12, 2006
Programmable logic devices with skewed clocking signals
ALTERA CORP45 citations96
US7191426B1Mar 13, 2007
Method and apparatus for performing incremental compilation on field programmable gate arrays
ALTERA CORP27 citations93
US7500216B1Mar 3, 2009
Method and apparatus for performing physical synthesis hill-climbing on multi-processor machines
ALTERA CORP42 citations92
US7360190B1Apr 15, 2008
Method and apparatus for performing retiming on field programmable gate arrays
ALTERA CORP25 citations92
US7290239B1Oct 30, 2007
Method and apparatus for performing post-placement functional decomposition for field programmable gate arrays
ALTERA CORP18 citations91
US7257800B1Aug 14, 2007
Method and apparatus for performing logic replication in field programmable gate arrays
ALTERA CORP28 citations91
US7290240B1Oct 30, 2007
Leveraging combinations of synthesis, placement and incremental optimizations
ALTERA CORP25 citations88
US9548740B1Jan 17, 2017
Multiple alternate configurations for an integrated circuit device
ALTERA CORP12 citations84
US9515658B1Dec 6, 2016
Method and apparatus for implementing configurable streaming networks
ALTERA CORP8 citations84
US9100012B1Aug 4, 2015
Adaptable programs using partial reconfiguration
ALTERA CORP13 citations84
US8856702B1Oct 7, 2014
Method and apparatus for performing multiple stage physical synthesis
ALTERA CORP5 citations84
US8732634B1May 20, 2014
Method and apparatus for performing fast incremental resynthesis
ALTERA CORP7 citations84
US7996797B1Aug 9, 2011
Method and apparatus for performing multiple stage physical synthesis
ALTERA CORP10 citations84
US7464286B1Dec 9, 2008
Programmable logic devices with skewed clocking signals
ALTERA CORP12 citations84
US7254801B1Aug 7, 2007
Synthesis aware placement: a novel approach that combines knowledge of possible resynthesis
ALTERA CORP15 citations84
US7594204B1Sep 22, 2009
Method and apparatus for performing layout-driven optimizations on field programmable gate arrays
ALTERA CORP8 citations83
US8806403B1Aug 12, 2014
Efficient configuration of an integrated circuit device using high-level language
ALTERA CORP9 citations82
US9922150B1Mar 20, 2018
Method and apparatus for satisfying operating conditions in a system design using an electronic design automation tool
ALTERA CORP8 citations81
US9690278B1Jun 27, 2017
Method and apparatus for high-level programs with general control flow
ALTERA CORP15 citations80
US8032855B1Oct 4, 2011
Method and apparatus for performing incremental placement on a structured application specific integrated circuit
ALTERA CORP9 citations76
US7620925B1Nov 17, 2009
Method and apparatus for performing post-placement routability optimization
ALTERA CORP7 citations74
US11171652B2Nov 9, 2021
Method and apparatus for implementing configurable streaming networks
ALTERA CORP2 citations73
US10615800B1Apr 7, 2020
Method and apparatus for implementing configurable streaming networks
ALTERA CORP2 citations73
US10366189B2Jul 30, 2019
Configuring a programmable device using high-level language
ALTERA CORP2 citations73
US9449132B2Sep 20, 2016
Configuring a programmable device using high-level language
ALTERA CORP4 citations73
US9703696B1Jul 11, 2017
Guided memory buffer allocation
ALTERA CORP5 citations71
US10033387B2Jul 24, 2018
Method apparatus for high-level programs with general control flow
ALTERA CORP2 citations69
US7797666B1Sep 14, 2010
Systems and methods for mapping arbitrary logic functions into synchronous embedded memories
ALTERA CORP2 citations63
US7509597B1Mar 24, 2009
Method and apparatus for performing post-placement functional decomposition on field programmable gate arrays using binary decision diagrams
ALTERA CORP5 citations63
US7444613B1Oct 28, 2008
Systems and methods for mapping arbitrary logic functions into synchronous embedded memories
ALTERA CORP4 citations63
US9147023B1Sep 29, 2015
Method and apparatus for performing fast incremental resynthesis
ALTERA CORP2 citations62
US7412677B1Aug 12, 2008
Detecting reducible registers
ALTERA CORP5 citations60
US10224934B1Mar 5, 2019
Method and apparatus for implementing configurable streaming networks
ALTERA CORP0 citations52
US9589090B1Mar 7, 2017
Method and apparatus for performing multiple stage physical synthesis
ALTERA CORP0 citations52
US7401314B1Jul 15, 2008
Method and apparatus for performing compound duplication of components on field programmable gate arrays
ALTERA CORP1 citations51
CHEN DORIS TZU LANG
4 patentsUS8296695B1Oct 23, 2012
Method and apparatus for performing fast incremental resynthesis
CHEN DORIS TZU LANG25 citations91
US8484596B1Jul 9, 2013
Method and apparatus for performing fast incremental resynthesis
CHEN DORIS TZU LANG6 citations83
US9134981B2Sep 15, 2015
OpenCL compilation
CHEN DORIS TZU LANG0 citations40
US8650525B2Feb 11, 2014
Integrated circuit compilation
CHEN DORIS TZU LANG0 citations40
CHIU GORDON RAYMOND
3 patentsUS8918748B1Dec 23, 2014
M/A for performing automatic latency optimization on system designs for implementation on programmable hardware
CHIU GORDON RAYMOND21 citations92
US8296696B1Oct 23, 2012
Method and apparatus for performing simultaneous register retiming and combinational resynthesis during physical synthesis
CHIU GORDON RAYMOND24 citations92
US8499201B1Jul 30, 2013
Methods and systems for measuring and presenting performance data of a memory controller system
CHIU GORDON RAYMOND25 citations90