Inventor
QUAN GABRIEL
CA17 patents
⚠️ This page may combine multiple inventors who share the name “QUAN GABRIEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ALTERA CORP
13 patentsUS9569574B1Feb 14, 2017
Method and apparatus for performing fast incremental physical design optimization
ALTERA CORP35 citations93
US7669157B1Feb 23, 2010
Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches
ALTERA CORP28 citations92
US7360190B1Apr 15, 2008
Method and apparatus for performing retiming on field programmable gate arrays
ALTERA CORP25 citations92
US7257800B1Aug 14, 2007
Method and apparatus for performing logic replication in field programmable gate arrays
ALTERA CORP28 citations91
US7194720B1Mar 20, 2007
Method and apparatus for implementing soft constraints in tools used for designing systems on programmable logic devices
ALTERA CORP19 citations91
US6779169B1Aug 17, 2004
Method and apparatus for placement of components onto programmable logic devices
ALTERA CORP32 citations91
US7594204B1Sep 22, 2009
Method and apparatus for performing layout-driven optimizations on field programmable gate arrays
ALTERA CORP8 citations83
US7464362B1Dec 9, 2008
Method and apparatus for performing incremental compilation
ALTERA CORP12 citations83
US7181717B1Feb 20, 2007
Method and apparatus for placement of components onto programmable logic devices
ALTERA CORP10 citations82
US11093672B2Aug 17, 2021
Method and apparatus for performing fast incremental physical design optimization
ALTERA CORP2 citations71
US10635772B1Apr 28, 2020
Method and apparatus for performing fast incremental physical design optimization
ALTERA CORP1 citations71
US9122826B1Sep 1, 2015
Method and apparatus for performing compilation using multiple design flows
ALTERA CORP0 citations52
US9754065B2Sep 5, 2017
Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices
ALTERA CORP1 citations51
BORER TERRY
3 patentsUS8589849B1Nov 19, 2013
Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices
BORER TERRY10 citations82
US8250505B1Aug 21, 2012
Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches
BORER TERRY5 citations72
US8589838B1Nov 19, 2013
M/A for performing incremental compilation using top-down and bottom-up design approaches
BORER TERRY1 citations61