Inventor
BORER TERRY
CA19 patents
⚠️ This page may combine multiple inventors who share the name “BORER TERRY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ALTERA CORP
16 patentsUS7669157B1Feb 23, 2010
Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches
ALTERA CORP28 citations92
US7360190B1Apr 15, 2008
Method and apparatus for performing retiming on field programmable gate arrays
ALTERA CORP25 citations92
US7594208B1Sep 22, 2009
Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage
ALTERA CORP18 citations91
US7257800B1Aug 14, 2007
Method and apparatus for performing logic replication in field programmable gate arrays
ALTERA CORP28 citations91
US7181703B1Feb 20, 2007
Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage
ALTERA CORP22 citations91
US7290240B1Oct 30, 2007
Leveraging combinations of synthesis, placement and incremental optimizations
ALTERA CORP25 citations88
US8370776B1Feb 5, 2013
Method and apparatus for compiling intellectual property systems design cores using an incremental compile design flow
ALTERA CORP14 citations84
US7254801B1Aug 7, 2007
Synthesis aware placement: a novel approach that combines knowledge of possible resynthesis
ALTERA CORP15 citations84
US7594204B1Sep 22, 2009
Method and apparatus for performing layout-driven optimizations on field programmable gate arrays
ALTERA CORP8 citations83
US7464362B1Dec 9, 2008
Method and apparatus for performing incremental compilation
ALTERA CORP12 citations83
US7370295B1May 6, 2008
Directed design space exploration
ALTERA CORP14 citations83
US8037435B1Oct 11, 2011
Directed design space exploration
ALTERA CORP2 citations61
US7389489B1Jun 17, 2008
Techniques for editing circuit design files to be compatible with a new programmable IC
ALTERA CORP6 citations54
US9122826B1Sep 1, 2015
Method and apparatus for performing compilation using multiple design flows
ALTERA CORP0 citations52
US9754065B2Sep 5, 2017
Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices
ALTERA CORP1 citations51
US7401314B1Jul 15, 2008
Method and apparatus for performing compound duplication of components on field programmable gate arrays
ALTERA CORP1 citations51
BORER TERRY
3 patentsUS8589849B1Nov 19, 2013
Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices
BORER TERRY10 citations82
US8250505B1Aug 21, 2012
Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches
BORER TERRY5 citations72
US8589838B1Nov 19, 2013
M/A for performing incremental compilation using top-down and bottom-up design approaches
BORER TERRY1 citations61