Inventor
BROWN STEPHEN D
CA26 patents
⚠️ This page may combine multiple inventors who share the name “BROWN STEPHEN D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ALTERA CORP
15 patentsUS7669157B1Feb 23, 2010
Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches
ALTERA CORP28 citations92
US7500216B1Mar 3, 2009
Method and apparatus for performing physical synthesis hill-climbing on multi-processor machines
ALTERA CORP42 citations92
US7194720B1Mar 20, 2007
Method and apparatus for implementing soft constraints in tools used for designing systems on programmable logic devices
ALTERA CORP19 citations91
US6779169B1Aug 17, 2004
Method and apparatus for placement of components onto programmable logic devices
ALTERA CORP32 citations91
US8856702B1Oct 7, 2014
Method and apparatus for performing multiple stage physical synthesis
ALTERA CORP5 citations84
US7996797B1Aug 9, 2011
Method and apparatus for performing multiple stage physical synthesis
ALTERA CORP10 citations84
US7594204B1Sep 22, 2009
Method and apparatus for performing layout-driven optimizations on field programmable gate arrays
ALTERA CORP8 citations83
US7464362B1Dec 9, 2008
Method and apparatus for performing incremental compilation
ALTERA CORP12 citations83
US7181717B1Feb 20, 2007
Method and apparatus for placement of components onto programmable logic devices
ALTERA CORP10 citations82
US7197734B1Mar 27, 2007
Method and apparatus for designing systems using logic regions
ALTERA CORP12 citations78
US7620925B1Nov 17, 2009
Method and apparatus for performing post-placement routability optimization
ALTERA CORP7 citations74
US7318210B1Jan 8, 2008
Method and apparatus for performing incremental placement for layout-driven optimizations on field programmable gate arrays
ALTERA CORP8 citations72
US9589090B1Mar 7, 2017
Method and apparatus for performing multiple stage physical synthesis
ALTERA CORP0 citations52
US9122826B1Sep 1, 2015
Method and apparatus for performing compilation using multiple design flows
ALTERA CORP0 citations52
US9754065B2Sep 5, 2017
Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices
ALTERA CORP1 citations51
BORER TERRY
3 patentsUS8589849B1Nov 19, 2013
Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices
BORER TERRY10 citations82
US8250505B1Aug 21, 2012
Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches
BORER TERRY5 citations72
US8589838B1Nov 19, 2013
M/A for performing incremental compilation using top-down and bottom-up design approaches
BORER TERRY1 citations61