Inventor
LIVINGSTONE WILLIAM J
US6 patents
Patents
6 patentsUS6725439B1Apr 20, 2004
Method of automated design and checking for ESD robustness
IBM44 citations89
US7684969B2Mar 23, 2010
Forming statistical model of independently variable parameters for timing analysis
IBM10 citations82
US7464359B2Dec 9, 2008
Method for re-routing an interconnection array to improve switching behavior in a single net and an associated interconnection array structure
IBM5 citations61
US7725850B2May 25, 2010
Methods for design rule checking with abstracted via obstructions
IBM5 citations60
US9104832B1Aug 11, 2015
Identifying and mitigating electromigration failures in signal nets of an integrated circuit chip design
IBM3 citations58
US7750648B2Jul 6, 2010
Method to quickly estimate inductance for timing models
IBM0 citations51