Inventor
SRIPADA SUBRAMANYAM
US14 patents
⚠️ This page may combine multiple inventors who share the name “SRIPADA SUBRAMANYAM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SYNOPSYS INC
9 patentsUS7739098B2Jun 15, 2010
System and method for providing distributed static timing analysis with merged results
SYNOPSYS INC21 citations85
US7900165B2Mar 1, 2011
Determining a design attribute by estimation and by calibration of estimated value
SYNOPSYS INC11 citations82
US8924906B2Dec 30, 2014
Determining a design attribute by estimation and by calibration of estimated value
SYNOPSYS INC3 citations61
US7216317B2May 8, 2007
Hierarchical signal integrity analysis using interface logic models
SYNOPSYS INC4 citations61
US9489478B2Nov 8, 2016
Simplifying modes of an electronic circuit by reducing constraints
SYNOPSYS INC2 citations52
US12406127B2Sep 2, 2025
Static timing analysis of multi-die three-dimensional integrated circuits
SYNOPSYS INC0 citations51
US7523428B2Apr 21, 2009
Hierarchical signal integrity analysis using interface logic models
SYNOPSYS INC1 citations51
US12488169B1Dec 2, 2025
Performing timing constraint equivalence checking on circuit designs
SYNOPSYS INC0 citations50
US10339258B2Jul 2, 2019
Look-ahead timing prediction for multi-instance module (MIM) engineering change order (ECO)
SYNOPSYS INC0 citations48
SRIPADA SUBRAMANYAM
4 patentsUS8627262B2Jan 7, 2014
Automatic generation of merged mode constraints for electronic circuits
SRIPADA SUBRAMANYAM5 citations68
US8473886B2Jun 25, 2013
Parallel parasitic processing in static timing analysis
SRIPADA SUBRAMANYAM4 citations59
US8701074B2Apr 15, 2014
Automatic reduction of modes of electronic circuits for timing analysis
SRIPADA SUBRAMANYAM3 citations58
US8607186B2Dec 10, 2013
Automatic verification of merged mode constraints for electronic circuits
SRIPADA SUBRAMANYAM4 citations58