Inventor

DOYLE BRIAN

US95 patents

⚠️ This page may combine multiple inventors who share the name “DOYLE BRIAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DOYLE BRIAN

INTEL CORP

Quantum wire gate device and method of making same

Carbon nanotube energy well (CNEW) field effect transistor

Method for capacitively coupling electronic devices

Metal-gate electrode for CMOS transistor applications

Work function tuning for MOSFET gate electrodes

Silicon-on-insulator devices and method for producing the same

Methods for uniform doping of non-planar transistor structures

Double-gate transistor with enhanced carrier mobility

Method for forming a High dielectric constant insulator in the fabrication of an integrated circuit

U-gate transistors and methods of fabrication

Nonplanar device with thinned lower body portion and method of fabrication

High mobility tri-gate devices and methods of fabrication

Quantum wire gate device and method of making same

Method for forming a high dielectric constant insulator in the fabrication of an integrated circuit

Methods for inducing strain in non-planar transistor structures

Semiconductor device having a laterally modulated gate workfunction and method of fabrication

Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby

Semiconductor device having a laterally modulated gate workfunction and method of fabrication

Floating-body dynamic random access memory and method of fabrication in tri-gate technology

Metal-gate electrode for CMOS transistor applications

Transistor structure having silicide source/drain extensions

Apparatus for capacitively coupling electronic devices

Method of making asymmetrical transistor structures

Capping layer in interconnect system and method for bonding the capping layer onto the interconnect system

Shielded structures to protect semiconductor devices

Method of making MOSFET gate electrodes with tuned work function

Method for tuning a work function for MOSFET gate electrodes

Method of creating shielded structures to protect semiconductor devices

Hardmask gate patterning technique for all transistors using spacer gate approach for critical dimension control

Electronic fabric with incorporated chip and interconnect

Trigate static random-access memory with independent source and drain engineering, and devices made therefrom

Metalgate electrode for PMOS transistor

Transistor for non volatile memory devices having a carbon nanotube channel and electrically floating quantum dots in its gate dielectric

Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby

Transistor for non volatile memory devices having a carbon nanotube channel and electrically floating quantum dots in its gate dielectric

Low resistance gate electrode layer and method of making same

Method of creating shielded structures to protect semiconductor devices

Method for bonding and debonding films using a high-temperature polymer

Apparatus and methods for improving multi-gate device performance

Floating-body dynamic random access memory and method of fabrication in tri-gate technology

Carbon nanotube energy well (CNEW) field effect transistor

MOS devices with reduced fringing capacitance

Multi-level magnetic tunnel junction (MTJ) devices including mobile magnetic skyrmions or ferromagnetic domains

SHAH UDAY

Nonplanar device with thinned lower body portion and method of fabrication

Nonplanar device with thinned lower body portion and method of fabrication

OGUZ KAAN

Perpendicular MTJ stacks with magnetic anisotropy enhancing layer and crystallization barrier layer

Perpendicular MTJ stacks with magnetic anisotropy enhancing layer and crystallization barrier layer

DIGITAL EQUIPMENT CORP

Hot carrier-hard gate oxides by nitrogen implantation before gate oxidation

DOYLE BRIAN

Device and method for performing exercises using a freely rotating ball

JIN BEEN-YIH

Method to introduce uniaxial strain in multigate nanoscale transistors by self aligned SI to SIGE conversion processes and structures formed thereby