Inventor

ONG SHIANG YANG

SG23 patents

⚠️ This page may combine multiple inventors who share the name “ONG SHIANG YANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ONG SHIANG YANG

GLOBALFOUNDRIES SG PTE LTD

Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations

Semiconductor device with reduced contact resistance and method of manufacturing thereof

Isolation scheme for high voltage device

High voltage Schottky diode and manufacturing method thereof

Low on resistance high voltage metal oxide semiconductor transistor

Integrated circuits with deep trench isolations and methods for producing the same

Selective STI stress relaxation through ion implantation

Trench isolation structures and methods of making thereof

Methods for fabricating integrated circuits with the implantation of nitrogen

Laterally-diffused metal-oxide-semiconductor devices with a multiple-thickness buffer dielectric layer

Methods for fabricating integrated circuits with the implantation of fluorine

Deep trench isolation structures with a substrate connection

Contact structures to deep trench isolation structures and method of nanufacturing the same

CHARTERED SEMICONDUCTOR MFG

End of range (EOR) secondary defect engineering using substitutional carbon doping

Selective STI stress relaxation through ion implantation

End of range (EOR) secondary defect engineering using chemical vapor deposition (CVD) substitutional carbon doping

Nested and isolated transistors with reduced impedance difference

HOENTSCHEL JAN

Late in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations

Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations

Methods of forming highly scaled semiconductor devices using a disposable spacer technique

TOH ENG HUAT

Semiconductor device with reduced contact resistance and method of manufacturing thereof

PANDEY SHESH MANI

Methods of tailoring work function of semiconductor devices with high-k/metal layer gate structures by performing a fluorine implant process

WIDODO JOHNNY

Nested and isolated transistors with reduced impedance difference