Inventor

EICHENBERGER ALEXANDRE E

US74 patents

⚠️ This page may combine multiple inventors who share the name “EICHENBERGER ALEXANDRE E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

EICHENBERGER ALEXANDRE E

EICHENBERGER ALEXANDRE E

Selective code generation optimization for an advanced dual-representation polyhedral loop transformation framework

Matrix multiplication operations using pair-wise load and splat operations

Complex matrix multiplication operations with data pre-conditioning in a high performance computing architecture

Matrix multiplication operations with data pre-conditioning in a high performance computing architecture

Checkpointing in speculative versioning caches

Framework for generating mixed-mode operations in loop-level simdization

Method and structure of using SIMD vector architectures to implement matrix multiplication

Domain stretching for an advanced dual-representation polyhedral loop transformation framework

All-to-all permutation of vector elements based on a permutation pattern encoded in mantissa and exponent bits in a floating-point SIMD architecture

Runtime dependence-aware scheduling using assist thread

Insertion of operation-and-indicate instructions for optimized SIMD code

SIMD code generation for loops with mixed data lengths

SIMD code generation in the presence of optimized misaligned data reorganization

Efficient data reorganization to satisfy data alignment constraints

System and method for advanced polyhedral loop transformations of source code in a compiler

Building approximate data dependences with a moving window

SIMD compare instruction using permute logic for distributed register files

Analyze and reduce number of data reordering operations in SIMD code

Tracking and detecting thread dependencies using speculative versioning cache

Systems, methods and computer products for cross-thread scheduling

Management of conditional branches within a data parallel system

Parallelization of irregular reductions via parallel building and exploitation of conflict-free units of work at runtime

Constant time worker thread allocation via configuration caching

Optimized scalar promotion with load and splat SIMD instructions

Method using SLP packing with statements having both isomorphic and non-isomorphic expressions

Optimized scalar promotion with load and splat SIMD instructions

Efficient code generation using loop peeling for SIMD loop code with multile misaligned statements

Method to exploit superword-level parallelism using semi-isomorphic packing

Data parallel function call for determining if called routine is data parallel

Data parallel function call for determining if called routine is data parallel

IBM

Aligning precision converted vector data using mask indicating offset relative to element boundary corresponding to precision type

Method to efficiently prefetch and batch compiler-assisted software cache accesses

Framework for efficient code generation using loop peeling for SIMD loop code with multiple misaligned statements

Efficient data reorganization to satisfy data alignment constraints

Framework for integrated intra- and inter-loop aggregation of contiguous memory accesses for SIMD vectorization

Optimized software cache lookup for SIMD architectures

Stable transitions in the presence of conditionals for an advanced dual-representation polyhedral loop transformation framework

Workload partitioning in a parallel system with hetergeneous alignment constraints

Efficient generation of SIMD code in presence of multi-threading and other false sharing conditions and in machines having memory protection support

SIMD code generation in the presence of optimized misaligned data reorganization

SIMD code generation for loops with mixed data lengths

Schedulers with load-store queue awareness

Optimizing branch re-wiring in a software instruction cache

Framework for integrated intra- and inter-loop aggregation of contiguous memory accesses for SIMD vectorization

Method and apparatus for eliminating the need for register assignment, allocation, spilling and re-filling

AYGUADE EDUARD

Data transfer optimized software cache for irregular memory references

Data transfer optimized software cache for regular memory references

ASAAD SAMEH

Multi-petascale highly efficient parallel supercomputer

GLOBALFOUNDRIES INC

Multi-petascale highly efficient parallel supercomputer

CHEN TONG

Optimized code generation targeting a high locality software cache