Inventor

BARROSO LUIZ ANDRE

US26 patents

⚠️ This page may combine multiple inventors who share the name “BARROSO LUIZ ANDRE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BARROSO LUIZ ANDRE

GOOGLE INC

Non-volatile random access memory in computer primary memory

Computer and data center load determination

System and method for providing load balanced processing

Low latency thread context caching

Managing power between data center loads

Server farm diagnostic and status system

Modulating processsor core operations

Shared input/output (I/O) unit

HEWLETT PACKARD DEVELOPMENT CO

Scalable architecture based on single-chip multiprocessing

Scalable architecture based on single-chip multiprocessing

Method and system for exclusive two-level caching in a chip-multiprocessor

Scalable multiprocessor system and cache coherence method incorporating invalid-to-dirty requests

Scalable multiprocessor system and cache coherence method implementing store-conditional memory transactions while an associated directory entry is encoded as a coarse bit vector

Method and system for detecting and resolving virtual address synonyms in a two-level cache hierarchy

System for minimizing directory information in scalable multiprocessor systems with logically independent input/output nodes

Method and system for exclusive two-level caching in a chip-multiprocessor

WEBER WOLF-DIETRICH

Load control in a data center

Powering a data center

Computer and data center load determination

Data center load monitoring for utilizing an access power amount based on a projected peak power usage and a monitored power usage

Load control in a data center

Computer and data center load determination

GOOGLE LLC

Computer and data center load determination

Data center design

Low latency thread context caching

CARLSON ANDREW B

Data center design