Inventor
GOPALAKRISHNAN PRAKASH
US11 patents
⚠️ This page may combine multiple inventors who share the name “GOPALAKRISHNAN PRAKASH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
GOPALAKRISHNAN PRAKASH
5 patentsUS8261228B1Sep 4, 2012
Technique for modeling parasitics from layout during circuit design and for parasitic aware circuit design using modes of varying accuracy
GOPALAKRISHNAN PRAKASH42 citations94
US8694933B2Apr 8, 2014
Methods, systems, and articles of manufacture for implementing electronic circuit designs with simulation awareness
GOPALAKRISHNAN PRAKASH5 citations82
US8612921B1Dec 17, 2013
Technique for modeling parasitics from layout during circuit design and for parasitic aware circuit design using modes of varying accuracy
GOPALAKRISHNAN PRAKASH6 citations80
US8584072B1Nov 12, 2013
Technique for modeling parasitics from layout during circuit design and for parasitic aware circuit design using modes of varying accuracy
GOPALAKRISHNAN PRAKASH9 citations80
US8527928B1Sep 3, 2013
Optimizing circuit layouts by configuring rooms for placing devices
GOPALAKRISHNAN PRAKASH2 citations58
CADENCE DESIGN SYSTEMS INC
4 patentsUS7665054B1Feb 16, 2010
Optimizing circuit layouts by configuring rooms for placing devices
CADENCE DESIGN SYSTEMS INC27 citations89
US6874133B2Mar 29, 2005
Integrated circuit design layout compaction method
CADENCE DESIGN SYSTEMS INC14 citations82
US7533358B2May 12, 2009
Integrated sizing, layout, and extractor tool for circuit design
CADENCE DESIGN SYSTEMS INC4 citations62
US7584440B2Sep 1, 2009
Method and system for tuning a circuit
CADENCE DESIGN SYSTEMS INC1 citations49