Inventor

ABATCHEV MIRZAFER K

US36 patents

⚠️ This page may combine multiple inventors who share the name “ABATCHEV MIRZAFER K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ABATCHEV MIRZAFER K

MICRON TECHNOLOGY INC

Mask material conversion

Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures

Method for integrated circuit fabrication using pitch multiplication

Pitch reduced patterns relative to photolithography features

Method for integrated circuit fabrication using pitch multiplication

Pitch reduced patterns relative to photolithography features

Method for integrated circuit fabrication using pitch multiplication

Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures

Method for integrated circuit fabrication using pitch multiplication

Critical dimension control for integrated circuits

Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same

Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same

Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same

Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures

Trim process for critical dimension control for integrated circuits

Trim process for critical dimension control for integrated circuits

Critical dimension control for integrated circuits

Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same

Plasma etching system and method

Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same

Mask material conversion

Plasma etching system and method

TRAN LUAN

Integrated circuit having pitch reduced patterns relative to photoithography features

Pitch reduced patterns relative to photolithography features

Pitch reduced patterns relative to photolithography features

ROUND ROCK RES LLC

Pitch reduced patterns relative to photolithography features

Pitch reduced patterns relative to photolithography features

ABATCHEV MIRZAFER K

Method for integrated circuit fabrication using pitch multiplication

Mask material conversion

LAM RES CORP

Negative ion control for dielectric etch

Silicon-based deposition for semiconductor processing

LODESTAR LICENSING GROUP LLC

Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same

Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same

ZHOU BAOSUO

Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same

WELLS DAVID H

Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures

MARAKHATANOV ALEXEI

Negative ion control for dielectric etch