Inventor

OHSAWA TAKASHI

JP177 patents

⚠️ This page may combine multiple inventors who share the name “OHSAWA TAKASHI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

OHSAWA TAKASHI

TOSHIBA KK

Semiconductor memory device

Semiconductor integrated circuit device

Semiconductor memory device

Semiconductor memory device with floating storage bulk region and method of manufacturing the same

Semiconductor memory device

Semiconductor memory device

Semiconductor memory device

Semiconductor memory device

DRAM having a power supply voltage lowering circuit

Dynamic semiconductor memory device

Semiconductor memory device and method of manufacturing the same

Semiconductor device

DRAM having a power supply voltage lowering circuit

Semiconductor integrated circuit device

Semiconductor memory device

Semiconductor memory device

Semiconductor memory device having internal voltage booster circuit coupled to bit line charging/equalizing circuit

DRAM having a power supply voltage lowering circuit

Semiconductor integrated circuit for generating an internal power source voltage with reduced potential changes

Voltage stress test circuit for a DRAM

Delay circuit for semiconductor integrated circuit devices

Semiconductor memory device with an error correction function

Semiconductor memory device having a floating storage bulk region

Floating body cell memory and reading and writing circuit thereof

Semiconductor memory device

Semiconductor storage device and semiconductor integrated circuit

Semiconductor memory device and semiconductor device

Semiconductor memory device and method of controlling the same

DRAM device with function of producing wordline drive signal based on stored charge in capacitor

Semiconductor memory device having voltage booster circuit

Dynamic semiconductor memory device with banks capable of operating independently

Multiplexer

Semiconductor memory device having folded bit line array and an open bit line array with imbalance correction

High speed, low noise CMOS multiplexer with precharge

Semiconductor memory device having voltage booster circuit coupled to a bit line charging/equalizing circuit or switch

Semiconductor integrated circuit for generating constant internal voltage

Semiconductor memory device with redundancy circuit

Semiconductor memory having built-in voltage stress test mode

Semiconductor memory with built-in parallel bit test mode

MOS random access memory device with an internal voltage-down converting transistor

Semiconductor memory apparatus

Dynamic type semiconductor memory device

Cmos ecl/ttl output circuit

Dynamic type random-access memory having improved timing characteristics

TTL to CMOS buffer circuit

Intermediate potential generation circuit for generating a potential intermediate between a power source potential and ground potential

Semiconductor memory device and manufacturing method thereof

MITSUBISHI ELECTRIC CORP

Discharge lamp lighting device capable of preventing a flicker due to arc movement

High intensity discharge lamp ballast apparatus

TANABE SEIYAKU CO

Method of preparing a controlled release liquid pharmaceutical composition