Inventor
KUNDU SANDIP
US13 patents
⚠️ This page may combine multiple inventors who share the name “KUNDU SANDIP”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
9 patentsUS6938225B2Aug 30, 2005
Scan design for double-edge-triggered flip-flops
INTEL CORP63 citations95
US6510398B1Jan 21, 2003
Constrained signature-based test
INTEL CORP68 citations92
US7197721B2Mar 27, 2007
Weight compression/decompression system
INTEL CORP16 citations83
US7096397B2Aug 22, 2006
Dft technique for avoiding contention/conflict in logic built-in self-test
INTEL CORP12 citations80
US6715091B1Mar 30, 2004
System for rearranging plurality of memory storage elements in a computer process to different configuration upon entry into a low power mode of operation
INTEL CORP11 citations73
US9520877B2Dec 13, 2016
Apparatus and method for detecting or repairing minimum delay errors
INTEL CORP3 citations72
US6912701B2Jun 28, 2005
Method and apparatus for power supply noise modeling and test pattern development
INTEL CORP3 citations62
US6973422B1Dec 6, 2005
Method and apparatus for modeling and circuits with asynchronous behavior
INTEL CORP4 citations61
US7036063B2Apr 25, 2006
Generalized fault model for defects and circuit marginalities
INTEL CORP1 citations50
IBM
4 patentsUS5796751AAug 18, 1998
Technique for sorting high frequency integrated circuits
IBM45 citations92
US5629858AMay 13, 1997
CMOS transistor network to gate level model extractor for simulation, verification and test generation
IBM21 citations92
US5793777AAug 11, 1998
System and method for testing internal nodes of an integrated circuit at any predetermined machine cycle
IBM6 citations73
US5297151AMar 22, 1994
Adjustable weighted random test pattern generator for logic circuits
IBM19 citations72