Inventor
GALIVANCHE RAJESH
US3 patents
Patents
3 patentsUS6510398B1Jan 21, 2003
Constrained signature-based test
INTEL CORP68 citations92
US7096397B2Aug 22, 2006
Dft technique for avoiding contention/conflict in logic built-in self-test
INTEL CORP12 citations80
US7861116B2Dec 28, 2010
Device, system, and method for optimized concurrent error detection
INTEL CORP1 citations45