Inventor

HAYES JERRY D

US32 patents

⚠️ This page may combine multiple inventors who share the name “HAYES JERRY D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HAYES JERRY D

IBM

Circuit and method for modeling I/O

Method and system for evaluating timing in an integrated circuit

Method and system for evaluating timing in an integrated circuit

Method and apparatus for statistical CMOS device characterization

Slack sensitivity to parameter variation based timing analysis

System and method for AC performance tuning by thereshold voltage shifting in tubbed semiconductor technology

Variable sigma adjust methodology for static timing

Delay-based bias temperature instability recovery measurements for characterizing stress degradation and recovery

Characterization circuit for fast determination of device capacitance variation

Slack sensitivity to parameter variation based timing analysis

Method of generating wiring routes with matching delay in the presence of process variation

System and method of analyzing timing effects of spatial distribution in circuits

Method of generating wiring routes with matching delay in the presence of process variation

Ring oscillator structure and method of separating random and systematic tolerance values

Slack sensitivity to parameter variation based timing analysis

Method and system for performing shapes correction of a multi-cell reticle photomask design

Method and system for evaluating timing in an integrated circuit

Method and apparatus for statistical CMOS device characterization

Method of generating wiring routes with matching delay in the presence of process variation

Array-based early threshold voltage recovery characterization measurement

Method and apparatus for measuring statistics of dram parameters with minimum perturbation to cell layout and environment

Method and apparatus for performing input/output floor planning on an integrated circuit design

Method and apparatus for statistical CMOS device characterization

System and method of analyzing timing effects of spatial distribution in circuits

AGARWAL KANAK B

Configurable PSRO structure for measuring frequency dependent capacitive loads

Measurement methodology and array structure for statistical stress and test of reliabilty structures

Parallel array architecture for constant current electro-migration stress testing

Method and test system for fast determination of parameter variation statistics

GEBARA FADI H

Test circuit for bias temperature instability recovery measurements

Test circuit for bias temperature instability recovery measurements

CULP JAMES A

Characterization of long range variability

AGARWAL KANAK BEHARI

On-chip measurement of signals