Inventor

MUFF ADAM JAMES

US40 patents

⚠️ This page may combine multiple inventors who share the name “MUFF ADAM JAMES”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MUFF ADAM JAMES

IBM

Execution unit with data dependent conditional write instructions

Processing unit incorporating vectorizable execution unit

Dual independent and shared resource vector execution units with shared register file

Processing unit incorporating L1 cache bypass

Load misaligned vector with permute and mask insert

Computer system architecture for a processor connected to a high speed bus transceiver

Processing unit incorporating multirate execution unit

Simultaneous multi-thread instructions issue to execution units while substitute injecting sequence of instructions for long latency sequencer instruction via multiplexer

Early exit processing of iterative refinement algorithm using register dependency disable

Early exit processing of iterative refinement algorithm using register dependency disable and programmable early exit condition

Processing unit incorporating special purpose register for use with instruction-based persistent vector multiplexer control

Processing unit incorporating instruction-based persistent vector multiplexer control

Reallocation of spatial index traversal between processing elements in response to changes in ray tracing graphics workload

Designating operands with fewer bits in instruction code by indexing into destination register history table for each thread

Operand multiplexor control modifier instruction in a fine grain multithreaded vector microprocessor

MICROSOFT TECHNOLOGY LICENSING LLC

No miss cache structure for real-time image transformations with data compression

Low power DMA snoop and skip

No miss cache structure for real-time image transformations with multiple LSR processing engines

Selective application of reprojection processing on layer sub-regions for optimizing late stage reprojection power

No miss cache structure for real-time image transformations with multiple LSR processing engines

No miss cache structure for real-time image transformations

System and method for classifying pixels

No miss cache structure for real-time image transformations with data compression

Interfacing with superconducting circuitry

Low power DMA labeling

Selectively applying reprojection processing to multi-layer scenes for optimizing late stage reprojection power

MUFF ADAM JAMES

Execution unit with inline pseudorandom number generator

Execution unit with inline pseudorandom number generator

Floating point execution unit for calculating a one minus dot product value in a single pass

Implementing a floating point weighted average function

Method and apparatus for implementing a multiple operand vector floating point summation to scalar function

COMPARAN MIGUEL

Anisotropic texture filtering with texture data prefetching

Anisotropic texture filtering with texture data prefetching

Method and apparatus for executing instructions

MEJDRICH ERIC OLIVER

Single precision vector dot product with “word” vector write mask

Single precision vector permute immediate with “word” vector write mask

Area efficient transcendental estimate algorithm

LUICK DAVID ARNOLD

Scalar precision float implementation on the “W” lane of vector unit

Store misaligned vector with permute

HICKEY MARK JOSEPH

Implied storage operation decode using redundant target address detection