Inventor

KOUFATY DAVID A

US38 patents

⚠️ This page may combine multiple inventors who share the name “KOUFATY DAVID A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KOUFATY DAVID A

INTEL CORP

Method and apparatus for suspending execution of a thread until a specified memory access occurs

Coherency techniques for suspending execution of a thread until a specified memory access occurs

Enforcing memory operand types using protection keys

Techniques for managing access to hardware accelerator memory

Remote atomic operations in multi-socket systems

Predicting contention in a processor

System for address mapping and translation protection

System for address mapping and translation protection

Remote atomic operations in multi-socket systems

Enforcing memory operand types using protection keys

Application driven hardware cache management

Virtual machine manager for address mapping and translation protection

Access control for memory protection key architecture

Spatial and temporal merging of remote atomic operations

Method for booting a heterogeneous system and presenting a symmetric core view

Apparatus and method for heterogeneous processors mapping to virtual cores

System partitioning to present software as platform level functionality via inter-partition bridge including reversible mode logic to switch between initialization, configuration, and execution mode

Hetergeneous processor apparatus and method

Selective migration of workloads between heterogeneous compute elements based on evaluation of migration performance benefit and available energy and thermal budgets

Apparatus and method for intelligently powering heterogeneous processor components

Memory protection at a thread level for a memory protection key architecture

Memory region access management

Technologies for increasing link efficiency

Remote atomic operations in multi-socket systems

Spatial and temporal merging of remote atomic operations

Memory domains protection method and apparatus with composite protection key numbers

Hetergeneous processor apparatus and method

Techniques to support mulitple interconnect protocols for an interconnect

Application driven hardware cache management

System, apparatus and method for accessing multiple address spaces via a data mover

Method for booting a heterogeneous system and presenting a symmetric core view

Technologies for protecting dynamically generated managed code with protection domains

Memory protection key architecture with independent user and supervisor domains

GINZBURG BORIS

Providing an asymmetric multicore processor system transparently to an operating system

SAHITA RAVI L

System for address mapping and translation protection

NAVEH ALON

Migrating tasks between asymmetric computing elements of a multi-core processor

TOLOPKA STEPHEN J

System partitioning to present software as platform level functionality including mode logic to maintain and enforce partitioning in first and configure partitioning in second mode

DIXON MARTIN G

Steering system management code region accesses