Inventor

BOGGS DARRELL D

US43 patents

⚠️ This page may combine multiple inventors who share the name “BOGGS DARRELL D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BOGGS DARRELL D

INTEL CORP

Multi-threading for a processor utilizing a replay queue

Breaking replay dependency loops in a processor using a rescheduled replay queue

Method and apparatus for generating a microinstruction responsive to the specification of an operand, in addition to a microinstruction based on the opcode, of a macroinstruction

Processor with registers storing committed/speculative data and a RAT state history recovery mechanism with retire pointer

Method and apparatus for rescheduling multiple micro-operations in a processor using a replay queue and a counter

Storing of instructions relating to a stalled thread

Computer processor with a replay system

Computer processor with a replay system having a plurality of checkers

Mechanism for efficiently overlapping multiple operand types in a microprocessor

Method and apparatus for maintaining a macro instruction for refetching in a pipelined processor

Microprocessor with novel instruction for signaling event occurrence and for providing event handling information in response thereto

Methods and apparatus for determining the next instruction pointer in an out-of-order execution computer system

Method and apparatus for managing resources in a multithreaded processor

Branch ordering buffer

Method and apparatus for assigning thread priority in a processor or the like

Determination of approaching instruction starvation of threads based on a plurality of conditions

Branch recovery mechanism to reduce processor front end stall time by providing path information for both correct and incorrect instructions mixed in the instruction pool

Multi-threading techniques for a processor utilizing a replay queue

Processor with a replay system that includes a replay queue for improved throughput

Prediction of load-store dependencies in a processing agent

Interface to a memory system for a processor having a replay system

Instruction pointer limits in processor that performs speculative out-of-order instruction execution

Decoding circuit and method providing immediate data for a micro-operation issued from a decoder

Decoder having independently loaded micro-alias and macro-alias registers accessible simultaneously by one micro-operation

Method and apparatus for conditionally generating a microinstruction that selects one of two values based upon control states of a microprocessor

Method for state recovery during assist and restart in a decoder having an alias mechanism

Determining whether thread fetch operation will be blocked due to processing of another thread

Control word register renaming

Method and system for an INUSE field resource management scheme

Programmable event driven yield mechanism which may activate service threads

Interface to a memory system for a processor having a replay system

Method and apparatus for providing address-size backward compatibility in a processor using segmented memory

Method and apparatus for assigning thread priority in a processor or the like

Method and apparatus for assigning thread priority in a processor or the like

Method and system for an INUSE field resource management scheme

NVIDIA CORP

Memory type which is cacheable yet inaccessible by speculative instructions

Lazy runahead operation for a microprocessor

Dynamic configuration of processing pipeline based on determined type of fetched instruction

Lazy runahead operation for a microprocessor

Queued instruction re-dispatch after runahead

Managing potentially invalid results during runahead

STEXAR CORP

Microprocessor with customer code store

BURNS DAVID W

Method and apparatus for assigning thread priority in a processor or the like