Inventor
DAS SABYASACHI
US31 patents
⚠️ This page may combine multiple inventors who share the name “DAS SABYASACHI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
XILINX INC
22 patentsUS10192016B2Jan 29, 2019
Neural network based physical synthesis for circuit designs
XILINX INC49 citations90
US10303648B1May 28, 2019
Logical and physical optimizations for partial reconfiguration design flow
XILINX INC11 citations83
US9646126B1May 9, 2017
Post-routing structural netlist optimization for circuit designs
XILINX INC7 citations83
US9483597B1Nov 1, 2016
Opportunistic candidate path selection during physical optimization of a circuit design for an IC
XILINX INC12 citations83
US8984462B1Mar 17, 2015
Physical optimization for timing closure for an integrated circuit
XILINX INC8 citations83
US10496777B1Dec 3, 2019
Physical synthesis for multi-die integrated circuit technology
XILINX INC7 citations82
US9773083B1Sep 26, 2017
Post-placement and pre-routing processing of critical paths in a circuit design
XILINX INC6 citations73
US9965581B1May 8, 2018
Fanout optimization to facilitate timing improvement in circuit designs
XILINX INC6 citations72
US9767247B1Sep 19, 2017
Look-up table restructuring for timing closure in circuit designs
XILINX INC2 citations72
US9613173B1Apr 4, 2017
Interactive multi-step physical synthesis
XILINX INC4 citations72
US9235660B1Jan 12, 2016
Selective addition of clock buffers to a circuit design
XILINX INC3 citations72
US10699053B1Jun 30, 2020
Timing optimization of memory blocks in a programmable IC
XILINX INC5 citations69
US9836568B1Dec 5, 2017
Programmable integrated circuit design flow using timing-driven pipeline analysis
XILINX INC6 citations69
US10540463B1Jan 21, 2020
Placement of delay circuits for avoiding hold violations
XILINX INC3 citations66
US10068045B1Sep 4, 2018
Programmable logic device design implementations with multiplexer transformations
XILINX INC4 citations66
US10572621B1Feb 25, 2020
Physical synthesis within placement
XILINX INC1 citations62
US10565334B1Feb 18, 2020
Targeted delay optimization through programmable clock delays
XILINX INC1 citations61
US10839125B1Nov 17, 2020
Post-placement and post-routing physical synthesis for multi-die integrated circuits
XILINX INC1 citations59
US10242150B1Mar 26, 2019
Circuit design implementation using control-set based merging and module-based replication
XILINX INC1 citations59
US10528697B1Jan 7, 2020
Timing-closure methodology involving clock network in hardware designs
XILINX INC0 citations52
US10970446B1Apr 6, 2021
Automated pipeline insertion on a bus
XILINX INC0 citations51
US10642951B1May 5, 2020
Register pull-out for sequential circuit blocks in circuit designs
XILINX INC0 citations37
DAS SABYASACHI
3 patentsUS9043735B1May 26, 2015
Synthesis of fast squarer functional blocks
DAS SABYASACHI4 citations71
US8407277B1Mar 26, 2013
Full subtractor cell for synthesis of area-efficient subtractor and divider
DAS SABYASACHI5 citations71
US8707225B1Apr 22, 2014
Synthesis of area-efficient subtractor and divider functional blocks
DAS SABYASACHI3 citations61