Inventor
OLAC-VAW ROMAN W
US18 patents
Patents
18 patentsUS11335601B2May 17, 2022
Non-planar I/O and logic semiconductor devices having different workfunction on common substrate
INTEL CORP6 citations85
US10892192B2Jan 12, 2021
Non-planar I/O and logic semiconductor devices having different workfunction on common substrate
INTEL CORP5 citations83
US10692771B2Jun 23, 2020
Non-planar I/O and logic semiconductor devices having different workfunction on common substrate
INTEL CORP4 citations83
US10229853B2Mar 12, 2019
Non-planar I/O and logic semiconductor devices having different workfunction on common substrate
INTEL CORP4 citations83
US10950606B2Mar 16, 2021
Dual fin endcap for self-aligned gate edge (SAGE) architectures
INTEL CORP2 citations73
US11823954B2Nov 21, 2023
Non-planar I/O and logic semiconductor devices having different workfunction on common substrate
INTEL CORP2 citations72
US10756210B2Aug 25, 2020
Depletion mode gate in ultrathin FINFET based architecture
INTEL CORP3 citations72
US9947585B2Apr 17, 2018
Multi-gate transistor with variably sized fin
INTEL CORP5 citations72
US12191207B2Jan 7, 2025
Non-planar I/O and logic semiconductor devices having different workfunction on common substrate
INTEL CORP0 citations62
US11075286B2Jul 27, 2021
Hybrid finfet structure with bulk source/drain regions
INTEL CORP0 citations62
US10964690B2Mar 30, 2021
Resistor between gates in self-aligned gate edge architecture
INTEL CORP1 citations62
US10930729B2Feb 23, 2021
Fin-based thin film resistor
INTEL CORP0 citations62
US10892261B2Jan 12, 2021
Metal resistor and self-aligned gate edge (SAGE) architecture having a metal resistor
INTEL CORP1 citations62
US11967615B2Apr 23, 2024
Dual threshold voltage (VT) channel devices and their methods of fabrication
INTEL CORP0 citations51
US10854757B2Dec 1, 2020
FINFET based junctionless wrap around structure
INTEL CORP0 citations51
US10164115B2Dec 25, 2018
Non-linear fin-based devices
INTEL CORP0 citations51
US10761264B2Sep 1, 2020
Transmission lines using bending fins from local stress
INTEL CORP0 citations50
US10784378B2Sep 22, 2020
Ultra-scaled fin pitch having dual gate dielectrics
INTEL CORP0 citations40