Inventor

CHANG HSU-YU

US33 patents

⚠️ This page may combine multiple inventors who share the name “CHANG HSU-YU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHANG HSU-YU

INTEL CORP

Gate-all-around integrated circuit structures having depopulated channel structures

Co-integrated high performance nanoribbon transistors with high voltage thick gate finFET devices

Gate-all-around integrated circuit structures having dual nanoribbon channel structures

Depletion mode gate in ultrathin FINFET based architecture

Multi-gate transistor with variably sized fin

Transistor gate metal with laterally graduated work function

Nanoribbon thick gate devices with differential ribbon spacing and width for SOC applications

Adjacent gate-all-around integrated circuit structures having non-merged epitaxial source or drain regions

Hybrid finfet structure with bulk source/drain regions

Resistor between gates in self-aligned gate edge architecture

Fin-based thin film resistor

Transistor with thermal performance boost

Single gated 3D nanowire inverter for high density thick gate SoC applications

Gate-all-around integrated circuit structures having dual nanoribbon channel structures

Gate-all-around integrated circuit structures having dual nanoribbon channel structures

Single gated 3D nanowire inverter for high density thick gate SOC applications

Gate-all-around integrated circuit structures having depopulated channel structures

Monolithic splitter using re-entrant poly silicon waveguides

Gate endcap architectures having relatively short vertical stack

Nanoribbon thick gate device with hybrid dielectric tuning for high breakdown and VT modulation

High voltage extended-drain MOS (EDMOS) nanowire transistors

Dual threshold voltage (VT) channel devices and their methods of fabrication

Isolation well doping with solid-state diffusion sources for finFET architectures

FINFET based junctionless wrap around structure

Doping with solid-state diffusion sources for finFET architectures

Doping with solid-state diffusion sources for finFET architectures

Non-linear fin-based devices

ESD diode solution for nanoribbon architectures

Multi voltage threshold transistors through process and design-induced multiple work functions

Transmission lines using bending fins from local stress

MOS antifuse with void-accelerated breakdown

UNIV NAT TAIWAN

Polysilicon thin film fabrication method

HAFEZ WALID M

Isolation well doping with solid-state diffusion sources for FinFET architectures