Inventor
KERAMIDAS GEORGIOS
GR21 patents
⚠️ This page may combine multiple inventors who share the name “KERAMIDAS GEORGIOS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
THINK SILICON RESEARCH AND TECH SINGLE MEMBER S A
11 patentsUS12554313B2Feb 17, 2026
Techniques for neural network execution utilizing memoization
THINK SILICON RESEARCH AND TECH SINGLE MEMBER S A0 citations61
US12481347B2Nov 25, 2025
Techniques for optimizing neural networks for memoization using shifted value localization
THINK SILICON RESEARCH AND TECH SINGLE MEMBER S A0 citations61
US12099396B2Sep 24, 2024
Techniques for optimizing neural networks for memoization using value localization
THINK SILICON RESEARCH AND TECH SINGLE MEMBER S A0 citations61
US12086311B2Sep 10, 2024
Gaze and content aware rendering logic
THINK SILICON RESEARCH AND TECH SINGLE MEMBER S A0 citations60
US11550389B1Jan 10, 2023
Gaze and content aware rendering logic
THINK SILICON RESEARCH AND TECH SINGLE MEMBER S A0 citations60
US12461855B2Nov 4, 2025
System and method for memory bandwidth reduction using a programmable cache line
THINK SILICON RESEARCH AND TECH SINGLE MEMBER S A0 citations55
US12136149B2Nov 5, 2024
Techniques for rendering vector graphics using precomputed textures
THINK SILICON RESEARCH AND TECH SINGLE MEMBER S A0 citations55
US11893667B2Feb 6, 2024
Techniques for rendering vector graphics using precomputed textures
THINK SILICON RESEARCH AND TECH SINGLE MEMBER S A0 citations55
US12470724B2Nov 11, 2025
Fixed-size block compression techniques for RGB channels
THINK SILICON RESEARCH AND TECH SINGLE MEMBER S A0 citations53
US12432361B2Sep 30, 2025
Fixed-size image alpha channel compression techniques
THINK SILICON RESEARCH AND TECH SINGLE MEMBER S A0 citations53
US12387386B2Aug 12, 2025
System and method for improving graphical user interface rendering
THINK SILICON RESEARCH AND TECH SINGLE MEMBER S A0 citations45
THINK SILICON SA
7 patentsUS9899007B2Feb 20, 2018
Adaptive lossy framebuffer compression with controllable error rate
THINK SILICON SA6 citations82
US9640149B2May 2, 2017
Methods for fixed rate block based compression of image data
THINK SILICON SA7 citations80
US10565677B2Feb 18, 2020
System and method for adaptive z-buffer compression in low power GPUS and improved memory operations with performance tracking
THINK SILICON SA2 citations70
US9658851B2May 23, 2017
Device and method for approximate memoization
THINK SILICON SA4 citations70
US10748510B2Aug 18, 2020
Framebuffer compression with controllable error rate
THINK SILICON SA2 citations67
US11107180B2Aug 31, 2021
Asymmetric multi-core heterogeneous parallel processing system with content aware and display aware rendering logic
THINK SILICON SA1 citations60
US10510133B2Dec 17, 2019
Asymmetric multi-core heterogeneous parallel processing system
THINK SILICON SA0 citations39
THINK SILICON LTD
2 patentsUS9110814B2Aug 18, 2015
Device and method for eliminating complex operations in processing systems based on caching
THINK SILICON LTD9 citations80
US9202308B2Dec 1, 2015
Methods of and apparatus for assigning vertex and fragment shading operations to a multi-threaded multi-format blending device
THINK SILICON LTD3 citations57