Inventor
SIDIROPOULOS GEORGE
GR12 patents
⚠️ This page may combine multiple inventors who share the name “SIDIROPOULOS GEORGE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
THINK SILICON SA
7 patentsUS9899007B2Feb 20, 2018
Adaptive lossy framebuffer compression with controllable error rate
THINK SILICON SA6 citations82
US9640149B2May 2, 2017
Methods for fixed rate block based compression of image data
THINK SILICON SA7 citations80
US10565677B2Feb 18, 2020
System and method for adaptive z-buffer compression in low power GPUS and improved memory operations with performance tracking
THINK SILICON SA2 citations70
US9658851B2May 23, 2017
Device and method for approximate memoization
THINK SILICON SA4 citations70
US10748510B2Aug 18, 2020
Framebuffer compression with controllable error rate
THINK SILICON SA2 citations67
US11107180B2Aug 31, 2021
Asymmetric multi-core heterogeneous parallel processing system with content aware and display aware rendering logic
THINK SILICON SA1 citations60
US10510133B2Dec 17, 2019
Asymmetric multi-core heterogeneous parallel processing system
THINK SILICON SA0 citations39
THINK SILICON LTD
2 patentsUS9110814B2Aug 18, 2015
Device and method for eliminating complex operations in processing systems based on caching
THINK SILICON LTD9 citations80
US9202308B2Dec 1, 2015
Methods of and apparatus for assigning vertex and fragment shading operations to a multi-threaded multi-format blending device
THINK SILICON LTD3 citations57