Inventor

JAIRATH SUMTI

US67 patents

⚠️ This page may combine multiple inventors who share the name “JAIRATH SUMTI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JAIRATH SUMTI

SAMBANOVA SYSTEMS INC

Configuration load of a reconfigurable data processor

Virtualization of a reconfigurable data processor

Inter-node buffer-based streaming for reconfigurable processor-as-a-service (RPaaS)

Dataflow function offload to reconfigurable processors

Dataflow all-reduce for reconfigurable processor systems

Compiler flow logic for reconfigurable architectures

Lossless tiling in convolution networks—tiling configuration

Instrumentation profiling for reconfigurable processors

Configuration of a reconfigurable data processor using sub-files

Performance estimation-based resource allocation for reconfigurable architectures

Quiesce reconfigurable data processor

Runtime execution of functions across reconfigurable processor

Executing a neural network graph using a non-homogenous set of reconfigurable processors

Inter-processor execution of configuration files on reconfigurable processors using smart network interface controller (SmartNIC) buffers

Inter-node execution of configuration files on reconfigurable processors using smart network interface controller (smartnic) buffers

Runtime execution of configuration files on reconfigurable processors with varying configuration granularity

Lossless tiling in convolution networks—weight gradient calculation

Lossless tiling in convolution networks—section boundaries

Intra-node buffer-based streaming for reconfigurable processor-as-a-service (RPaaS)

Anti-congestion flow control for reconfigurable processors

Lossless tiling in convolution networks—read-modify-write in backward pass

Tensor partitioning and partition access order

Lossless tiling in convolution networks—tiling configuration for a sequence of sections of a graph

Training a neural network using a non-homogenous set of reconfigurable processors

Inter-node execution of configuration files on reconfigurable processors using network interface controller (NIC) buffers

Compiler flow logic for reconfigurable architectures

Multi-headed multi-buffer for buffering data for processing

Virtualization of a reconfigurable data processor

Configuration unload of a reconfigurable data processor

Lossless tiling in convolution networks—materialization of tensors

Lossless tiling in convolution networks-backward pass

Runtime patching of configuration files

Lossless tiling in convolution networks—padding before tiling, location-based tiling, and zeroing-out

Performance estimation-based resource allocation for reconfigurable architectures

Lossless tiling in convolution networks—section boundaries

Lossless tiling in convolution networks—tiling configuration between two sections

Lossless tiling in convolution networks—padding and re-tilling at section boundaries

Lossless tiling in convolution networks—data flow logic

Top level network and array level network for reconfigurable data processors

Lossless tiling in convolution networks—section cuts

Lossless tiling in convolution networks—resetting overlap factor to zero at section boundaries

Lossless tiling in convolution networks—graph metadata generation

Efficient deconfiguration of a reconfigurable data processor

Quiesce reconfigurable data processor

Independent control of multiple concurrent application graphs in a reconfigurable data processor

Flow control for reconfigurable processors

Instrumentation networks for data flow graphs

Compile time instrumentation of data flow graphs

FEEHRER JOHN R

Interrupt processing unit for preventing interrupt loss

ORACLE INT CORP

Hardware message queues for intra-cluster communication