Inventor

AGNELLO PAUL D

US29 patents

⚠️ This page may combine multiple inventors who share the name “AGNELLO PAUL D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

AGNELLO PAUL D

IBM

Double gate trench transistor

Relaxed, low-defect SGOI for strained Si CMOS applications

Vertical trench-formed dual-gate FET device structure and method for creation

Double polysilicon process for providing single chip high performance logic and compact embedded memory structure

Method of forming a film for a multilayer Semiconductor device for improving thermal stability of cobalt silicide using platinum or nitrogen

Tasin oxygen diffusion barrier in multilayer structures

Plasma treatment to enhance inorganic dielectric adhesion to copper

Thin film for a multilayer semiconductor device for improving thermal stability and a method thereof

Method of fabricating semiconductor side wall fin

Relaxed, low-defect SGOI for strained Si CMOS applications

CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture

CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture

Semiconductor chip having both compact memory and high performance logic

Plasma treatment to enhance inorganic dielectric adhesion to copper

Comprehensive process for low temperature SI epit axial growth

Method for fabricating abrupt source/drain extensions with controllable gate electrode overlap

Comprehensive process for low temperature epitaxial growth

Salicide formation method

Method of fabricating semiconductor side wall fin

Method of fabricating semiconductor side wall fin

Method and structure of a dual/wrap-around gate field effect transistor

Method and apparatus for preventing rupture and contamination of an ultra-clean APCVD reactor during shutdown

Method and apparatus for preventing rupture and contamination of an ultra-clean APCVD reactor during shutdown

Plasma treatment to enhance inorganic dielectric adhesion to copper

Semiconductor device with abrupt source/drain extensions with controllable gate electrode overlap

Preventing cavitation in high aspect ratio dielectric regions of semiconductor device

Preventing cavitation in high aspect ratio dielectric regions of semiconductor device

Double gate trench transistor

AGNELLO PAUL D

Relaxed low-defect SGOI for strained SI CMOS applications