Inventor

DENNARD ROBERT H

US87 patents

⚠️ This page may combine multiple inventors who share the name “DENNARD ROBERT H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DENNARD ROBERT H

IBM

Relaxed, low-defect SGOI for strained Si CMOS applications

Threshold voltage roll-off compensation using back-gated MOSFET devices for system high-performance and low standby power

High density chip carrier with integrated passive devices

High density chip carrier with integrated passive devices

Fabrication of defect free silicon on an insulating substrate

Single cycle read/write/writeback pipeline, full-wordline I/O DRAM architecture with enhanced write and single ended sensing

Method of fabricating defect-free silicon on an insulating substrate

Low power interface circuit

CMOS off-chip driver with reduced signal swing and reduced power supply disturbance

Trench-capacitor-one-transistor storage cell and array for dynamic random access memories

Method to control device threshold of SOI MOSFET&#39;s

Memory cell having improved read stability

Method of making a device threshold control of front-gate silicon-on-insulator MOSFET using a self-aligned back-gate

Relaxed, low-defect SGOI for strained Si CMOS applications

Polysilicon back-gated SOI MOSFET for dynamic threshold voltage control

Method to control device threshold of SOI MOSFET&#39;s

Polysilicon back-gated SOI MOSFET for dynamic threshold voltage control

Memory with adiabatically switched bit lines

Sense amplifier circuits and high speed latch circuits using gated diodes

3T1D memory cells using gated diodes and methods of use thereof

Nondestructive read, two-switch, single-charge-storage device RAM devices

Floating wordline using a dynamic row decoder and bitline VDD precharge

High speed DRAM local bit line sense amplifier

Differential charge transfer sense amplifier

Sense amplifier threshold compensation

Methods of forming FINFETs with locally thinned channels from fins having in-situ doped epitaxial cladding

Method of lateral oxidation of NFET and PFET high-K gate stacks

Bulk finFET with super steep retrograde well

Substrate solution for back gate controlled SRAM with coexisting logic devices

Low power circuits with small voltage swing transmission, voltage regeneration, and wide bandwidth architecture

Silicon-on-insulator latch-up pulse-radiation detector

Low voltage single-input DRAM current-sensing amplifier

Low cost fabrication of double box back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layer

High speed latch circuits using gated diodes

Method of fabricating self-aligned contact vias

Field effect transistors with polycrystalline silicon gate self-aligned to both conductive and non-conductive regions and fabrication of integrated circuits containing the transistors

Field effect transistors and fabrication of integrated circuits containing the transistors

DENNARD ROBERT H

Power delivery in a heterogeneous 3-D stacked apparatus

Self-aligned well implant for improving short channel effects control, parasitic capacitance, and junction leakage

Voltage conversion and integrated circuits with stacked voltage domains

Voltage conversion and integrated circuits with stacked voltage domains

Hybrid double box back gate silicon-on-insulator wafers with enhanced mobility channels

Structure for CMOS ETSOI with multiple threshold voltages and active well bias capability

Isolation structures for SOI devices with ultrathin SOI and ultrathin box

Power delivery in a heterogeneous 3-D stacked apparatus

Switched capacitor voltage converters

CAI JIN

ETSOI CMOS with back gates

Complementary bipolar inverter

ETSOI CMOS with back gates

CHANG LELAND

Low voltage signaling

Method to control device threshold of SOI MOSFET's

Method to control device threshold of SOI MOSFET's