Inventor

FOGEL KEITH E

US226 patents

⚠️ This page may combine multiple inventors who share the name “FOGEL KEITH E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FOGEL KEITH E

IBM

Ultimate SIMOX

Test probe having elongated conductor embedded in an elostomeric material which is mounted on a space transformer

Three dimensional high performance interconnection package

Thermally conductive composite interface, cooled electronic assemblies employing the same, and methods of fabrication thereof

Relaxed, low-defect SGOI for strained Si CMOS applications

Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer

Coaxial vias in an electronic substrate

Method of forming a three dimensional high performance interconnection package

Connector assembly for chip testing

Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal

Method of creating high-quality relaxed SiGe-on-insulator for strained Si CMOS applications

Wafer scale epitaxial graphene transfer

Lattice matched aspect ratio trapping to reduce defects in III-V layer directly grown on silicon

Formation of large scale single crystalline graphene

Laser processing method for trench-edge-defect-free solid phase epitaxy in confined geometrics

Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer

Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal

Relaxed, low-defect SGOI for strained Si CMOS applications

Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal

Patterned SOI by oxygen implantation and annealing

Use of hydrogen implantation to improve material properties of silicon-germanium-on-insulator material made by thermal diffusion

Method of improving the quality of defective semiconductor material

Land grid array fabrication using elastomer core and conducting metal shell or mesh

Interconnections for flip-chip using lead-free solders and having reaction barrier layers

Patterned strained silicon for high performance circuits

Formation of patterned silicon-on-insulator (SOI)/silicon-on-nothing (SON) composite structure by porous Si engineering

Interposer with electrical contact button and method

MOSFET with ultra low drain leakage

Deep high capacity capacitor for bulk substrates

Programmable buried antifuse

Leakage-free implantation-free ETSOI transistors

Designable channel FinFET fuse

Method of making a gallium nitride device

Epitaxial oxide fin segments to prevent strained semiconductor fin end relaxation

Protective capping layer for spalled gallium nitride

MOSFET with ultra low drain leakage

III-V device structure with multiple threshold voltage

Defect reduction with rotated double aspect ratio trapping

FinFET device with vertical silicide on recessed source/drain epitaxy regions

Doped zinc oxide as N+ layer for semiconductor devices

Controlled spalling of group III nitrides containing an embedded spall releasing plane

GLOBALFOUNDRIES INC

Implant-free punch through doping layer formation for bulk FinFET structures

Formation of large scale single crystalline graphene

Multiple via structure and method

Formation of large scale single crystalline graphene

BEDELL STEPHEN W

Thin substrate fabrication using stress-induced substrate spalling

Thin substrate fabrication using stress-induced spalling

INTERNAT MACHINES CORP

Formation of SOI by oxidation of silicon with engineered porosity gradient

ADAM THOMAS N

Merged fin finFET with (100) sidewall surfaces and method of making same

FOGEL KEITH E

Transparent conductive electrode for three dimensional photovoltaic device