Inventor · disambiguated record
Richard Blinne
Also filed as: BLINNE RICHARD · BLINNE RICHARD D
13 granted patents·1 pending application·264 citations·filing 1990–2008
93Inventor score
Technology areasG06F
Top patents by PatentIndex Score
14 records- 0177US6662349B2Method of repeater insertion for hierarchical integrated circuit designLSI LOGIC CORP·Filed 2002·Granted Dec 9, 2003·26 cites·6 claims
- 0271US7111269B2Comparison of two hierarchical netlist to generate change orders for updating an integrated circuit layoutLSI LOGIC CORP·Filed 2003·Granted Sep 19, 2006·22 cites·26 claims
- 0371US5274568AMethod of estimating logic cell delay timeNCR CO·Filed 1990·Granted Dec 28, 1993·73 cites·24 claims
- 0470US7107559B2Method of partitioning an integrated circuit design for physical design verificationLSI LOGIC CORP·Filed 2003·Granted Sep 12, 2006·17 cites·12 claims
- 0568US7007248B2Method and apparatus for implementing engineering change ordersLSI LOGIC CORP·Filed 2003·Granted Feb 28, 2006·17 cites·19 claims
- 0666US7231626B2Method of implementing an engineering change order in an integrated circuit design by windowsLSI CORP·Filed 2004·Granted Jun 12, 2007·15 cites·8 claims
- 0762US5521834AMethod and apparatus for calculating dynamic power dissipation in CMOS integrated circuitsAT & T GLOBAL INF SOLUTION·Filed 1993·Granted May 28, 1996·37 cites·22 claims
- 0857US7219317B2Method and computer program for verifying an incremental change to an integrated circuit designLSI LOGIC CORP·Filed 2004·Granted May 15, 2007·6 cites·20 claims
- 0956US7260803B2Incremental dummy metal insertionsLSI CORP·Filed 2003·Granted Aug 21, 2007·7 cites·22 claims
- 1052US7302654B2Method of automating place and route corrections for an integrated circuit design from physical design validationLSI CORP·Filed 2004·Granted Nov 27, 2007·3 cites·8 claims
- 1149US7853901B2Unified layer stack architectureLSI CORP·Filed 2008·Granted Dec 14, 2010·0 cites·20 claims
- 1249US6141631APulse rejection circuit model program and technique in VHDLLSI LOGIC CORP·Filed 1998·Granted Oct 31, 2000·24 cites·14 claims
- 1345US5995730AMethod for generating format-independent electronic circuit representationsLSI LOGIC CORP·Filed 1997·Granted Nov 30, 1999·17 cites·33 claims
- 1444US2006090144A1Method of automating place and route corrections for an integrated circuit design from physical design validationLSI LOGIC CORP·Filed 2004·Application pending·0 cites
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