Inventor

ANDERSON ANDREW V

US109 patents

⚠️ This page may combine multiple inventors who share the name “ANDERSON ANDREW V”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ANDERSON ANDREW V

INTEL CORP

Method and apparatus for bandwidth-efficient and storage-efficient backups

Tracking memory page state

Memory device and system including a low power interface

System and method to deprivilege components of a virtual machine monitor

Method and apparatus for differential, bandwidth-efficient and storage-efficient backups

Automating tuning of speech recognition systems

Method and apparatus to enable efficient processing and transmission of network communications

Method for automatically and dynamically switching between speech technologies

Method and apparatus for interfacing to a computer memory

Combining N-best lists from multiple speech recognizers

DMA controller and coherency-tracking unit for efficient data transfers between coherent and non-coherent memory spaces

Synchronizing a translation lookaside buffer to an extended paging table

Method and apparatus for deriving travel profiles

Method and apparatus for fine grain memory protection

Chipset support for managing hardware interrupts in a virtual machine system

Chipset support for managing hardware interrupts in a virtual machine system

Method for improving speech recognition performance using speaker and channel information

Selecting one of multiple speech recognizers in a system based on performance predections resulting from experience

Mechanism for efficient low priority write draining

Monitoring the operation of a processor

Extended paging tables to map guest physical memory addresses from virtual memory page tables to host physical memory addresses in a virtual machine system

Method and apparatus for supporting address translation in a virtual machine environment

Method and apparatus for scheduling virtual machine access to shared resources

Use of multiple virtual machine monitors to handle privileged events

Method and apparatus for supporting address translation in a virtual machine environment

Providing support for single stepping a virtual machine in a virtual machine environment

Support for nested fault in a virtual machine environment

Control register access virtualization performance improvement in the virtual-machine architecture

Control over faults occurring during the operation of guest software in the virtual-machine architecture

Handling faults associated with operation of guest software in the virtual-machine architecture

Prefetch system for memory controller

Virtualizing memory type

Executing a protected device model in a virtual machine

Optimizing system behavior in a virtual machine environment

System and method for controlling switching between VMM and VM using enabling value of VMM timer indicator and VMM timer value having a specified time

Vectoring an interrupt or exception upon resuming operation of a virtual machine

BENNETT STEVEN M

Virtualization event processing in a layered virtualization architecture

Synchronizing a translation lookaside buffer with an extended paging table

Timer offsetting mechanism in a virtual machine environment

Virtualizing physical memory in a virtual machine system utilizing multilevel translation table base registers to map guest virtual addresses to guest physical addresses then to host physical addresses

Translating a guest virtual address to a host physical address as guest software executes on a virtual machine

Optimizing processor-managed resources based on the behavior of a virtual machine monitor

Optimizing processor-managed resources based on the behavior of a virtual machine monitor

Injecting virtualization events in a layered virtualization architecture

Interrupt processing in a layered virtualization architecture

RAMBUS INC

High performance cost optimized memory with delayed memory writes

Apparatus and method for bus timing compensation

Apparatus and method for refreshing subsets of memory devices in a memory system

NEIGER GILBERT

Delivering interrupts directly to a virtual processor

SAHITA RAVI L

Low latency virtual machine page table management